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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [controller_test.v] - Diff between revs 230 and 231
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| Rev 230 |
Rev 231 |
| Line 84... |
Line 84... |
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always @ (posedge clk_358 or negedge reset_n) begin
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always @ (posedge clk_358 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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vert_counter <= 6'd0;
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hor_counter <= 8'd0;
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hor_counter <= 8'd0;
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vert_counter = 9'd0;
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vert_counter <= 9'd0;
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end
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end
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else begin
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else begin
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if (hor_counter == 8'd227) begin // last colum
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if (hor_counter == 8'd227) begin // last colum
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hor_counter <= 8'd0;
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hor_counter <= 8'd0;
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