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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [stubs.v] - Diff between revs 252 and 255
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module ICP (PI, PO, PAD, Y);
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module ICP (PAD, PI, GND5O, GND5R, VDD5O, VDD5R, CLAMPC, PO, Y);
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input PAD;
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input PAD;
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input PI;
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input PI;
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output Y;
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input GND5O;
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input GND5R;
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input VDD5O;
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input VDD5R;
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input CLAMPC;
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output PO;
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output PO;
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output Y;
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endmodule
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endmodule
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module BBT16P (EN, PAD, A);
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module BT4P (A, EN, GND5O, GND5R, VDD5O, VDD5R, CLAMPC, PAD);
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input A;
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input A;
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input EN;
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input EN;
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input GND5O;
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input GND5R;
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input VDD5O;
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input VDD5R;
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input CLAMPC;
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output PAD;
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output PAD;
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endmodule
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endmodule
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module CORNERCLMP (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
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input CLAMPC;
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input VDD5O;
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input VDD5R;
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input GND5O;
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input GND5R;
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endmodule
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module GND5ALLPADP (VDD5O, VDD5R, CLAMPC, GND);
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input CLAMPC;
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input VDD5O;
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input VDD5R;
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input GND;
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endmodule
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module VDD5ALLPADP (GND5O, GND5R, CLAMPC, VDD);
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input CLAMPC;
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input GND5O;
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input GND5R;
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input VDD;
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endmodule
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module FILLERP_110 (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
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input CLAMPC;
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input VDD5O;
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input VDD5R;
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input GND5O;
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input GND5R;
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endmodule
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