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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 169 and 171

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Rev 169	Rev 171
Line 162...	Line 162...
`end`	`end`
`BRK_IMP :`	`BRK_IMP :`
`begin`	`begin`
`alu_status[B] <= 1;`	`alu_status[B] <= 1;`
`end`	`end`
`PLP_IMP : //, RTI_IMP :`	`PLP_IMP, RTI_IMP :`
`begin`	`begin`
`alu_status[C] <= alu_a[C];`	`alu_status[C] <= alu_a[C];`
`alu_status[Z] <= alu_a[Z];`	`alu_status[Z] <= alu_a[Z];`
`alu_status[I] <= alu_a[I];`	`alu_status[I] <= alu_a[I];`
`alu_status[D] <= alu_a[D];`	`alu_status[D] <= alu_a[D];`
Line 208...	Line 208...
`STATUS[D] = alu_status[D];`	`STATUS[D] = alu_status[D];`
`STATUS[Z] = alu_status[Z];`	`STATUS[Z] = alu_status[Z];`
`STATUS[N] = alu_status[N];`	`STATUS[N] = alu_status[N];`
`STATUS[5] = 1;`	`STATUS[5] = 1;`

	`bcdl = 0;`
	`bcdh = 0;`
	`bcdh2 = 0;`
	`AL = 0;`
	`AH = 0;`


`case (alu_opcode)`	`case (alu_opcode)`
`// BIT - Bit Test`	`// BIT - Bit Test`
`BIT_ZPG, BIT_ABS: begin`	`BIT_ZPG, BIT_ABS: begin`
`result = A & alu_a;`	`result = A & alu_a;`
`end`	`end`
Line 245...	Line 252...
`//NOP_IMP: begin`	`//NOP_IMP: begin`
`// Do nothing :-D`	`// Do nothing :-D`
`//end`	`//end`

`// PLP - Pull Processor Status Register`	`// PLP - Pull Processor Status Register`
`PLP_IMP : begin //, RTI_IMP: begin`	`PLP_IMP, RTI_IMP: begin`
`STATUS = alu_a;`	`STATUS = alu_a;`
`end`	`end`

`PLA_IMP : begin`	`PLA_IMP : begin`
`result = alu_a;`	`result = alu_a;`
Line 323...	Line 330...

`// ADC - Add with carry`	`// ADC - Add with carry`
`// TODO: verify synthesis for % operand`	`// TODO: verify synthesis for % operand`
`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`	`ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin`
`if (alu_status[D] == 1) begin`	`if (alu_status[D] == 1) begin`
`<<<<<<< .mine`	`//$display("MODO DECIMAL");`
`<<<<<<< .mine`
`bcdl = A[3:0] + alu_a[3:0] + alu_status[C];`
`bcdh = A[7:4] + alu_a[7:4];`

`$write("1: bcdl %d bcdh %d\n", bcdl, bcdh);`

`if (bcdl > 9) begin`
`//$write("\n %d \n", bcdl[6:4]);`
`bcdh = bcdh + bcdl[5:4];`
`bcdl = bcdl % 10;`
`=======`
`=======`
`$display("MODO DECIMAL");`
`>>>>>>> .r165`
`AL = A[3:0] + alu_a[3:0] + alu_status[C];`	`AL = A[3:0] + alu_a[3:0] + alu_status[C];`
`AH = A[7:4] + alu_a[7:4];`	`AH = A[7:4] + alu_a[7:4];`
`$display("AL = %h", AL);`	`//$display("AL = %d", AL);`
`$display("AH = %h", AH);`	`//$display("AH = %d", AH);`
`if (AL > 9) begin`	`if (AL > 9) begin`
`bcdh = AH + (AL / 10);`	`bcdh = AH + (AL / 10);`
`bcdl = AL % 10;`	`bcdl = AL % 10;`
`>>>>>>> .r164`
`end`	`end`
`if (AH > 9) begin`	`else begin`
`STATUS[C] = 1;`	`bcdh = AH;`
`bcdh2 = bcdh % 10;`	`bcdl = AL;`
`end`	`end`
`<<<<<<< .mine`
`<<<<<<< .mine`

`//$write("bcdl %d bcdh %d\n", bcdl, bcdh);`	`// ok`

	`if (bcdh > 9) begin`
`result = {bcdh[3:0],bcdl[3:0]};`	`STATUS[C] = 1;`
`=======`	`bcdh2 = bcdh % 10;`
`=======`	`end`
`$display("bcdh = %h", bcdh);`	`else begin`
`$display("bcdl = %h", bcdl);`	`STATUS[C] = 0;`
`>>>>>>> .r165`	`bcdh2 = bcdh;`
	`end`
	`//$display("bcdh2 = %d", bcdh2);`
	`//$display("bcdl = %d", bcdl);`
`result = {bcdh2[3:0],bcdl[3:0]};`	`result = {bcdh2[3:0],bcdl[3:0]};`
`<<<<<<< .mine`
`>>>>>>> .r164`
`=======`
`$display("result = %h", result);`
`>>>>>>> .r165`
`end`	`end`
`else begin`	`else begin`
`$display("MODO NORMAL");`	`//$display("MODO NORMAL");`
`{STATUS[C],result} = op1 + op2 + alu_status[C];`	`{STATUS[C],result} = op1 + op2 + alu_status[C];`
`end`	`end`

`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`	`if ((op1[7] == op2[7]) && (op1[7] != result[7]))`
`STATUS[V] = 1;`	`STATUS[V] = 1;`
Line 458...	Line 446...
`STATUS[V] = 1;`	`STATUS[V] = 1;`
`else`	`else`
`STATUS[V] = 0;`	`STATUS[V] = 0;`
`*/`	`*/`
`if (alu_status[D] == 1) begin`	`if (alu_status[D] == 1) begin`
`bcdl = A[3:0] - alu_a[3:0] - ( 1 - alu_status[C] );`	`bcdl = A[3:0] - alu_a[3:0] - ~alu_status[C];`
`bcdh = A[7:4] - alu_a[7:4];`	`bcdh = A[7:4] - alu_a[7:4];`
`if (bcdl > 9) begin`	`if (bcdl > 9) begin`
`bcdh = bcdh + bcdl[5:4];`	`bcdh = bcdh + bcdl[5:4];`
`bcdl = bcdl % 10;`	`bcdl = bcdl % 10;`
`end`	`end`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Diff between revs 169 and 171