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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Diff between revs 181 and 183

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Rev 181 Rev 183
Line 286... Line 286...
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[Z] = (alu_result_expected == 0) ? 1 : 0;
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[N] = alu_result_expected[7];
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                alu_status_expected[V] = ((alu_a[7] == sign) && (alu_a[7] != alu_result_expected[7]));
                check;
                check;
        end
        end
        $stop;
        //$stop;
        // CLD
        // CLD
        alu_opcode = CLD_IMP;
        alu_opcode = CLD_IMP;
        @(negedge clk);
        @(negedge clk);
        alu_status_expected[D] = 0;
        alu_status_expected[D] = 0;
        check;
        check;

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