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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 102 and 103
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| Rev 102 |
Rev 103 |
| Line 168... |
Line 168... |
{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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{page_crossed, address_plus_index[7:0]} = temp_addr[7:0] + index;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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address_plus_index[12:8] = temp_addr[12:8] + page_crossed;
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end
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end
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end
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end
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wire [8:0] sp_plus_one;
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assign sp_plus_one = sp + 9'b000000001;
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wire [8:0] sp_minus_one;
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assign sp_minus_one = sp - 9'b000000001;
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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always @ (posedge clk or negedge reset_n) begin // sequencial always block
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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// all registers must assume default values
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// all registers must assume default values
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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pc <= 0; // TODO: this is written somewhere. something about a reset vector. must be checked.
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sp <= 13'h100; // TODO: the default is not 0. maybe $0100 or something like that. must be checked.
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sp <= 9'b100000000; // the default is 'h100
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ir <= 8'h00;
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ir <= 8'h00;
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temp_addr <= 13'h00;
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temp_addr <= 13'h00;
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temp_data <= 8'h00;
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temp_data <= 8'h00;
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state <= RESET;
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state <= RESET;
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// registered outputs also receive default values
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// registered outputs also receive default values
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