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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 61 and 63

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Rev 61	Rev 63
Line 59...	Line 59...
`output reg [7:0] data_out;`	`output reg [7:0] data_out;`
`output reg [7:0] alu_opcode;`	`output reg [7:0] alu_opcode;`
`output reg [7:0] alu_a;`	`output reg [7:0] alu_a;`

`// FSM states`	`// FSM states`
`localparam FETCH_OP = 4'b000;`	`localparam FETCH_OP = 4'b0000;`
`localparam FETCH_LOW = 4'b0001;`	`localparam FETCH_LOW = 4'b0001;`
`localparam FETCH_HIGH = 4'b0010;`	`localparam FETCH_HIGH = 4'b0010;`
`localparam SET_PC = 4'b0011;`	`localparam SET_PC = 4'b0011;`
`localparam READ_EFFECTIVE = 4'b0100;`	`localparam READ_EFFECTIVE = 4'b0100;`
`localparam DO_OPERATION = 4'b0101;`	`localparam DO_OPERATION = 4'b0101;`
`localparam WRITE_DUMMY = 4'b0110;`	`localparam WRITE_DUMMY = 4'b0110;`
`localparam WRITE_EFFECTIVE = 4'b0110;`	`localparam WRITE_EFFECTIVE = 4'b0111;`
`localparam CALCULATE_INDEX = 4'b0111;`	`localparam CALCULATE_INDEX = 4'b1000;`
`localparam CHECK_FOR_PAGE_CROSS = 4'b1000;`	`localparam CHECK_FOR_PAGE_CROSS = 4'b1001;`

`// OPCODES TODO: verify how this get synthesised`	`// OPCODES TODO: verify how this get synthesised`
`include "../T6507LP_Package.v"	`include "../T6507LP_Package.v"

`// control signals`	`// control signals`
Line 106...	Line 106...
`reg jump;`	`reg jump;`

`reg enable;`	`reg enable;`

`wire [12:0] next_pc;`	`wire [12:0] next_pc;`
`assign next_pc = pc + 1'b1;`	`assign next_pc = pc + 13'b0000000000001;`

`always @ (posedge clk_in or negedge n_rst_in) begin`	`always @ (posedge clk_in or negedge n_rst_in) begin`
`if (n_rst_in == 1'b0) begin`	`if (n_rst_in == 1'b0) begin`
`// TODO: all registers must assume default values`	`// TODO: all registers must assume default values`

Line 426...	Line 426...
`LDY_ABX = 8'hBC;`	`LDY_ABX = 8'hBC;`
`*/`	`*/`


`end`	`end`
`end`	`end // no way`
`endmodule`	`endmodule`




`No newline at end of file`	`No newline at end of file`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Diff between revs 61 and 63