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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// T6507LP IP Core ////
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//// t6507 IP Core ////
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//// ////
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//// ////
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//// This file is part of the T6507LP project ////
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//// This file is part of the t6507 project ////
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//// http://www.opencores.org/cores/t6507lp/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6507 io wrapper ////
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//// I/O wrapper for the 6507 processor ////
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//// ////
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//// TODO: ////
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//// - Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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`include "stubs.v"
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`include "stubs.v"
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module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);
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module t6507lp_io(vdd, gnd, clk, reset_n, data_in, rw_mem, data_out, address, clkIO, reset_nIO, data_inIO, rw_memIO, data_outIO, addressIO);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd13;
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parameter [3:0] ADDR_SIZE = 4'd13;
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|
|
localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'b0001;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'b0001;
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|
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input vdd;
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input gnd;
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|
|
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input clk;
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input clk;
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output clkIO;
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wire clkIO;
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input reset_n;
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input reset_n;
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output reset_nIO;
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wire reset_nIO;
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input [DATA_SIZE_:0] data_in;
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input [DATA_SIZE_:0] data_in;
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output [DATA_SIZE_:0] data_inIO;
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reg [DATA_SIZE_:0] data_inIO;
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|
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output rw_mem;
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wire rw_memIO;
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output [DATA_SIZE_:0] data_out;
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reg [DATA_SIZE_:0] data_outIO;
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output [ADDR_SIZE_:0] address;
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reg [ADDR_SIZE_:0] addressIO;
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|
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wire clampc;
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wire pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, chainfinal;
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|
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input rw_mem;
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wire muxed;
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output rw_memIO;
|
|
|
|
input [DATA_SIZE_:0] data_out;
|
t6507lp t6507lp( //core
|
output [DATA_SIZE_:0] data_outIO;
|
.clk (clkIO),
|
|
.reset_n (reset_nIO),
|
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.data_in (data_inIO),
|
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.rw_mem (rw_memIO),
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.data_out (data_outIO),
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.address (addressIO)
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|
);
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|
|
|
assign muxed = (reset_nIO == 0) ? chainfinal : rw_memIO;
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|
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input [ADDR_SIZE_:0] address;
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wire dummy_vdd, dummy_gnd, dummy_clampc;
|
output [ADDR_SIZE_:0] addressIO;
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|
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// the ICP cell format is PAD PI Y PO
|
|
ICP clk_pad(
|
ICP clk_pad(
|
.PI (gnd),
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|
.PO (gnd),
|
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.PAD (clk),
|
.PAD (clk),
|
|
.PI (pipo9),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
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.VDD5R (dummy_vdd),
|
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.CLAMPC (dummy_clampc),
|
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.PO (chain_final),
|
.Y (clkIO)
|
.Y (clkIO)
|
);
|
);
|
|
|
ICP reset_n_pad(
|
ICP reset_n_pad(
|
.PI (gnd),
|
|
.PO (gnd),
|
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.PAD (reset_n),
|
.PAD (reset_n),
|
|
.PI (pipo8),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
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|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo9),
|
.Y (reset_nIO)
|
.Y (reset_nIO)
|
);
|
);
|
|
|
ICP data_in_pad0(
|
ICP data_in_pad0(
|
.PI (gnd),
|
|
.PO (gnd),
|
|
.PAD (data_in[0]),
|
.PAD (data_in[0]),
|
|
.PI (pipo7),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo8),
|
.Y (data_inIO[0])
|
.Y (data_inIO[0])
|
);
|
);
|
|
|
ICP data_in_pad1(
|
ICP data_in_pad1(
|
.PI (gnd),
|
|
.PO (gnd),
|
|
.PAD (data_in[1]),
|
.PAD (data_in[1]),
|
|
.PI (pipo6),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo7),
|
.Y (data_inIO[1])
|
.Y (data_inIO[1])
|
);
|
);
|
|
|
ICP data_in_pad2(
|
ICP data_in_pad2(
|
.PI (gnd),
|
|
.PO (gnd),
|
|
.PAD (data_in[2]),
|
.PAD (data_in[2]),
|
|
.PI (pipo5),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo6),
|
.Y (data_inIO[2])
|
.Y (data_inIO[2])
|
);
|
);
|
|
|
ICP data_in_pad3(
|
ICP data_in_pad3(
|
.PI (gnd),
|
|
.PO (gnd),
|
|
.PAD (data_in[3]),
|
.PAD (data_in[3]),
|
|
.PI (pipo4),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo5),
|
.Y (data_inIO[3])
|
.Y (data_inIO[3])
|
);
|
);
|
|
|
ICP data_in_pad4(
|
ICP data_in_pad4(
|
.PI (gnd),
|
|
.PO (gnd),
|
|
.PAD (data_in[4]),
|
.PAD (data_in[4]),
|
|
.PI (pipo3),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo4),
|
.Y (data_inIO[4])
|
.Y (data_inIO[4])
|
);
|
);
|
|
|
ICP data_in_pad5(
|
ICP data_in_pad5(
|
.PI (gnd),
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.PO (gnd),
|
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.PAD (data_in[5]),
|
.PAD (data_in[5]),
|
|
.PI (pipo2),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo3),
|
.Y (data_inIO[5])
|
.Y (data_inIO[5])
|
);
|
);
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|
|
ICP data_in_pad6(
|
ICP data_in_pad6(
|
.PI (gnd),
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|
.PO (gnd),
|
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.PAD (data_in[6]),
|
.PAD (data_in[6]),
|
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.PI (pipo1),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
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.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
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.PO (pipo2),
|
.Y (data_inIO[6])
|
.Y (data_inIO[6])
|
);
|
);
|
|
|
ICP data_in_pad7(
|
ICP data_in_pad7(
|
.PI (gnd),
|
|
.PO (gnd),
|
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.PAD (data_in[7]),
|
.PAD (data_in[7]),
|
|
.PI (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PO (pipo1),
|
.Y (data_inIO[7])
|
.Y (data_inIO[7])
|
);
|
);
|
|
|
BBT16P rw_mem_pad(
|
BT4P rw_mem_pad(
|
.EN (gnd),
|
.A (muxed),
|
.PAD (rw_memIO),
|
.EN (dummy_gnd),
|
.A (rw_mem)
|
.GND5O (dummy_gnd),
|
);
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
BBT16P data_out_pad0(
|
.VDD5R (dummy_vdd),
|
.EN (gnd),
|
.CLAMPC (dummy_clampc),
|
.PAD (data_outIO[0]),
|
.PAD (rw_mem)
|
.A (data_out[0])
|
);
|
);
|
|
|
BT4P data_out_pad0(
|
BBT16P data_out_pad1(
|
.A (data_outIO[0]),
|
.EN (gnd),
|
.EN (dummy_gnd),
|
.PAD (data_outIO[1]),
|
.GND5O (dummy_gnd),
|
.A (data_out[1])
|
.GND5R (dummy_gnd),
|
);
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
BBT16P data_out_pad2(
|
.CLAMPC (dummy_clampc),
|
.EN (gnd),
|
.PAD (data_out[0])
|
.PAD (data_outIO[2]),
|
);
|
.A (data_out[2])
|
|
);
|
BT4P data_out_pad1(
|
|
.A (data_outIO[1]),
|
BBT16P data_out_pad3(
|
.EN (dummy_gnd),
|
.EN (gnd),
|
.GND5O (dummy_gnd),
|
.PAD (data_outIO[3]),
|
.GND5R (dummy_gnd),
|
.A (data_out[3])
|
.VDD5O (dummy_vdd),
|
);
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
BBT16P data_out_pad4(
|
.PAD (data_out[1])
|
.EN (gnd),
|
);
|
.PAD (data_outIO[4]),
|
|
.A (data_out[4])
|
BT4P data_out_pad2(
|
);
|
.A (data_outIO[2]),
|
|
.EN (dummy_gnd),
|
BBT16P data_out_pad5(
|
.GND5O (dummy_gnd),
|
.EN (gnd),
|
.GND5R (dummy_gnd),
|
.PAD (data_outIO[5]),
|
.VDD5O (dummy_vdd),
|
.A (data_out[5])
|
.VDD5R (dummy_vdd),
|
);
|
.CLAMPC (dummy_clampc),
|
|
.PAD (data_out[2])
|
BBT16P data_out_pad6(
|
);
|
.EN (gnd),
|
|
.PAD (data_outIO[6]),
|
BT4P data_out_pad3(
|
.A (data_out[6])
|
.A (data_outIO[3]),
|
);
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
BBT16P data_out_pad7(
|
.GND5R (dummy_gnd),
|
.EN (gnd),
|
.VDD5O (dummy_vdd),
|
.PAD (data_outIO[7]),
|
.VDD5R (dummy_vdd),
|
.A (data_out[7])
|
.CLAMPC (dummy_clampc),
|
);
|
.PAD (data_out[3])
|
|
);
|
BBT16P adress_pad0(
|
|
.EN (gnd),
|
BT4P data_out_pad4(
|
.PAD (addressIO[0]),
|
.A (data_outIO[4]),
|
.A (address[0])
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (data_out[4])
|
|
);
|
|
|
|
BT4P data_out_pad5(
|
|
.A (data_outIO[5]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (data_out[5])
|
|
);
|
|
|
|
BT4P data_out_pad6(
|
|
.A (data_outIO[6]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (data_out[6])
|
|
);
|
|
|
|
BT4P data_out_pad7(
|
|
.A (data_outIO[7]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (data_out[7])
|
|
);
|
|
|
|
BT4P address_pad0(
|
|
.A (addressIO[0]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[0])
|
|
);
|
|
|
|
BT4P address_pad1(
|
|
.A (addressIO[1]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[1])
|
|
);
|
|
BT4P address_pad2(
|
|
.A (addressIO[2]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[2])
|
|
);
|
|
BT4P address_pad3(
|
|
.A (addressIO[3]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[3])
|
|
);
|
|
BT4P address_pad4(
|
|
.A (addressIO[4]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[4])
|
|
);
|
|
BT4P address_pad5(
|
|
.A (addressIO[5]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[5])
|
|
);
|
|
BT4P address_pad6(
|
|
.A (addressIO[6]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[6])
|
|
);
|
|
BT4P address_pad7(
|
|
.A (addressIO[7]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[7])
|
|
);
|
|
BT4P address_pad8(
|
|
.A (addressIO[8]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[8])
|
|
);
|
|
BT4P address_pad9(
|
|
.A (addressIO[9]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[9])
|
|
);
|
|
BT4P address_pad10(
|
|
.A (addressIO[10]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[10])
|
|
);
|
|
BT4P address_pad11(
|
|
.A (addressIO[11]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[11])
|
|
);
|
|
|
|
BT4P address_pad12(
|
|
.A (addressIO[12]),
|
|
.EN (dummy_gnd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.CLAMPC (dummy_clampc),
|
|
.PAD (address[12])
|
|
);
|
|
|
|
CORNERCLMP left_up_pad (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
|
);
|
|
|
|
CORNERCLMP left_down_pad (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
|
);
|
|
|
|
CORNERCLMP right_up_pad (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
|
);
|
|
|
|
CORNERCLMP right_down_pad (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
|
);
|
|
|
|
GND5ALLPADP gnd_pad_left (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND (dummy_gnd)
|
|
);
|
|
|
|
GND5ALLPADP gnd_pad_right (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND (dummy_gnd)
|
|
);
|
|
|
|
GND5ALLPADP gnd_pad_up (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND (dummy_gnd)
|
|
);
|
|
|
|
GND5ALLPADP gnd_pad_down (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND (dummy_gnd)
|
|
);
|
|
|
|
VDD5ALLPADP vdd_pad_left (
|
|
.CLAMPC (dummy_clampc),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD (dummy_vdd)
|
|
);
|
|
|
|
VDD5ALLPADP vdd_pad_right (
|
|
.CLAMPC (dummy_clampc),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD (dummy_vdd)
|
|
);
|
|
|
|
VDD5ALLPADP vdd_pad_up (
|
|
.CLAMPC (dummy_clampc),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD (dummy_vdd)
|
|
);
|
|
|
|
VDD5ALLPADP vdd_pad_down (
|
|
.CLAMPC (dummy_clampc),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd),
|
|
.VDD (dummy_vdd)
|
|
);
|
|
|
|
FILLERP_110 filler0 (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
|
);
|
|
|
|
FILLERP_110 filler1 (
|
|
.CLAMPC (dummy_clampc),
|
|
.VDD5O (dummy_vdd),
|
|
.VDD5R (dummy_vdd),
|
|
.GND5O (dummy_gnd),
|
|
.GND5R (dummy_gnd)
|
);
|
);
|
|
|
BBT16P adress_pad1(
|
|
.EN (gnd),
|
|
.PAD (addressIO[1]),
|
|
.A (address[1])
|
|
);
|
|
|
|
BBT16P adress_pad2(
|
|
.EN (gnd),
|
|
.PAD (addressIO[2]),
|
|
.A (address[2])
|
|
);
|
|
|
|
BBT16P adress_pad3(
|
|
.EN (gnd),
|
|
.PAD (addressIO[3]),
|
|
.A (address[3])
|
|
);
|
|
|
|
BBT16P adress_pad4(
|
|
.EN (gnd),
|
|
.PAD (addressIO[4]),
|
|
.A (address[4])
|
|
);
|
|
|
|
BBT16P adress_pad5(
|
|
.EN (gnd),
|
|
.PAD (addressIO[5]),
|
|
.A (address[5])
|
|
);
|
|
|
|
BBT16P adress_pad6(
|
|
.EN (gnd),
|
|
.PAD (addressIO[6]),
|
|
.A (address[6])
|
|
);
|
|
|
|
BBT16P adress_pad7(
|
|
.EN (gnd),
|
|
.PAD (addressIO[7]),
|
|
.A (address[7])
|
|
);
|
|
|
|
BBT16P adress_pad8(
|
|
.EN (gnd),
|
|
.PAD (addressIO[8]),
|
|
.A (address[8])
|
|
);
|
|
|
|
BBT16P adress_pad9(
|
|
.EN (gnd),
|
|
.PAD (addressIO[9]),
|
|
.A (address[9])
|
|
);
|
|
|
|
BBT16P adress_pad10(
|
|
.EN (gnd),
|
|
.PAD (addressIO[10]),
|
|
.A (address[10])
|
|
);
|
|
|
|
BBT16P adress_pad11(
|
|
.EN (gnd),
|
|
.PAD (addressIO[11]),
|
|
.A (address[11])
|
|
);
|
|
|
|
BBT16P adress_pad12(
|
|
.EN (gnd),
|
|
.PAD (addressIO[12]),
|
|
.A (address[12])
|
|
);
|
|
|
|
endmodule
|
endmodule
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
