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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Diff between revs 224 and 225

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`//// ////`	`//// ////`
`////////////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////////////`

`include "timescale.v"	`include "timescale.v"

`module vga_controller ( reset, clk_50, line, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);`	`module vga_controller ( reset, clk_50, line, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS);`

`input reset;`	`input reset;`
`input clk_50;`	`input clk_50;`
`input [8:0] SW;`	`input [8:0] SW;`
`input [479:0] line;`	`input [479:0] line;`
	`input [4:0] vert_counter;`
`output reg [3:0] VGA_R;`	`output reg [3:0] VGA_R;`
`output reg [3:0] VGA_G;`	`output reg [3:0] VGA_G;`
`output reg [3:0] VGA_B;`	`output reg [3:0] VGA_B;`
`output [9:0] LEDR;`	`output [9:0] LEDR;`
`output reg VGA_VS;`	`output reg VGA_VS;`
`output reg VGA_HS;`	`output reg VGA_HS;`


`reg clk_25;`	`reg clk_25;`
`reg [9:0] hc;`	`reg [9:0] hc;`
`reg [9:0] vc;`	`reg [9:0] vc;`
`reg vsenable;`	`reg vsenable;`
`wire vidon;`	`wire vidon;`

`assign LEDR = SW;`	`assign LEDR[8:0] = SW;`
	`assign LEDR[9] = reset;`

`always @ (posedge clk_50 or negedge reset)`	`always @ (posedge clk_50 or negedge reset)`
`begin`	`begin`
`if (!reset) begin`	`if (!reset) begin`
`clk_25 <= 0;`	`clk_25 <= 0;`
Line 140...	Line 141...
`end`	`end`

`always @ (posedge clk_25)`	`always @ (posedge clk_25)`
`begin`	`begin`
`if (vidon == 1) begin`	`if (vidon == 1) begin`
`if (hc < 320) begin`	`if (hc < 40) begin`
`if (vc < 240) begin`	`if (vert_counter < 10) begin`
	`/VGA_R[0] <= line[hc12];`
	`VGA_R[1] <= line[hc*12+1];`
	`VGA_R[2] <= line[hc*12+2];`
	`VGA_R[3] <= line[hc*12+3];`
	`VGA_G[0] <= line[hc*12+4];`
	`VGA_G[1] <= line[hc*12+5];`
	`VGA_G[2] <= line[hc*12+6];`
	`VGA_G[3] <= line[hc*12+7];`
	`VGA_B[0] <= line[hc*12+8];`
	`VGA_B[1] <= line[hc*12+9];`
	`VGA_B[2] <= line[hc*12+10];`
	`VGA_B[3] <= line[hc12+11];/`
`VGA_R[0] <= 1;`	`VGA_R[0] <= 1;`
`VGA_G[0] <= 1;`	`VGA_R[1] <= 0;`
`VGA_B[0] <= 1;`
`VGA_R[1] <= 1;`
`VGA_G[1] <= 1;`
`VGA_B[1] <= 1;`
`VGA_R[2] <= 1;`	`VGA_R[2] <= 1;`
	`VGA_R[3] <= 0;`
	`VGA_G[0] <= 1;`
	`VGA_G[1] <= 0;`
`VGA_G[2] <= 1;`	`VGA_G[2] <= 1;`
`VGA_B[2] <= 1;`	`VGA_G[3] <= 0;`
`VGA_R[3] <= 1;`
`VGA_G[3] <= 1;`
`VGA_B[3] <= 1;`
`end`
`else begin`
`VGA_R[0] <= 0;`
`VGA_G[0] <= 0;`
`VGA_B[0] <= 1;`	`VGA_B[0] <= 1;`
`VGA_R[1] <= 0;`	`VGA_B[1] <= 0;`
`VGA_G[1] <= 0;`
`VGA_B[1] <= 1;`
`VGA_R[2] <= 0;`
`VGA_G[2] <= 0;`
`VGA_B[2] <= 1;`	`VGA_B[2] <= 1;`
`VGA_R[3] <= 0;`	`VGA_B[3] <= 0;`
`VGA_G[3] <= 0;`
`VGA_B[3] <= 1;`
`end`
`end`	`end`
`else begin`	`else begin`
`if (vc < 240) begin`	`VGA_R[0] <= 0;`
`VGA_R[0] <= 1;`
`VGA_G[0] <= 0;`	`VGA_G[0] <= 0;`
`VGA_B[0] <= 0;`	`VGA_B[0] <= 0;`
`VGA_R[1] <= 1;`	`VGA_R[1] <= 0;`
`VGA_G[1] <= 0;`	`VGA_G[1] <= 0;`
`VGA_B[1] <= 0;`	`VGA_B[1] <= 0;`
`VGA_R[2] <= 1;`	`VGA_R[2] <= 0;`
`VGA_G[2] <= 0;`	`VGA_G[2] <= 0;`
`VGA_B[2] <= 0;`	`VGA_B[2] <= 0;`
`VGA_R[3] <= 1;`	`VGA_R[3] <= 0;`
`VGA_G[3] <= 0;`	`VGA_G[3] <= 0;`
`VGA_B[3] <= 0;`	`VGA_B[3] <= 0;`
`end`	`end`
	`end`
`else begin`	`else begin`
`VGA_R[0] <= 0;`	`VGA_R[0] <= 0;`
`VGA_G[0] <= 1;`	`VGA_G[0] <= 0;`
`VGA_B[0] <= 0;`	`VGA_B[0] <= 0;`
`VGA_R[1] <= 0;`	`VGA_R[1] <= 0;`
`VGA_G[1] <= 1;`	`VGA_G[1] <= 0;`
`VGA_B[1] <= 0;`	`VGA_B[1] <= 0;`
`VGA_R[2] <= 0;`	`VGA_R[2] <= 0;`
`VGA_G[2] <= 1;`	`VGA_G[2] <= 0;`
`VGA_B[2] <= 0;`	`VGA_B[2] <= 0;`
`VGA_R[3] <= 0;`	`VGA_R[3] <= 0;`
`VGA_G[3] <= 1;`	`VGA_G[3] <= 0;`
`VGA_B[3] <= 0;`	`VGA_B[3] <= 0;`
`end`	`end`
`end`
	`/* if (vc < 240) begin`
	`VGA_R[0] <= 1;`
	`VGA_G[0] <= 1;`
	`VGA_B[0] <= 1;`
	`VGA_R[1] <= 1;`
	`VGA_G[1] <= 1;`
	`VGA_B[1] <= 1;`
	`VGA_R[2] <= 1;`
	`VGA_G[2] <= 1;`
	`VGA_B[2] <= 1;`
	`VGA_R[3] <= 1;`
	`VGA_G[3] <= 1;`
	`VGA_B[3] <= 1;`
	`end`
	`else begin`
	`VGA_R[0] <= 0;`
	`VGA_G[0] <= 0;`
	`VGA_B[0] <= 1;`
	`VGA_R[1] <= 0;`
	`VGA_G[1] <= 0;`
	`VGA_B[1] <= 1;`
	`VGA_R[2] <= 0;`
	`VGA_G[2] <= 0;`
	`VGA_B[2] <= 1;`
	`VGA_R[3] <= 0;`
	`VGA_G[3] <= 0;`
	`VGA_B[3] <= 1;`
	`end`
	`end`
	`else begin`
	`if (vc < 240) begin`
	`VGA_R[0] <= 1;`
	`VGA_G[0] <= 0;`
	`VGA_B[0] <= 0;`
	`VGA_R[1] <= 1;`
	`VGA_G[1] <= 0;`
	`VGA_B[1] <= 0;`
	`VGA_R[2] <= 1;`
	`VGA_G[2] <= 0;`
	`VGA_B[2] <= 0;`
	`VGA_R[3] <= 1;`
	`VGA_G[3] <= 0;`
	`VGA_B[3] <= 0;`
	`end`
	`else begin`
	`VGA_R[0] <= 0;`
	`VGA_G[0] <= 1;`
	`VGA_B[0] <= 0;`
	`VGA_R[1] <= 0;`
	`VGA_G[1] <= 1;`
	`VGA_B[1] <= 0;`
	`VGA_R[2] <= 0;`
	`VGA_G[2] <= 1;`
	`VGA_B[2] <= 0;`
	`VGA_R[3] <= 0;`
	`VGA_G[3] <= 1;`
	`VGA_B[3] <= 0;`
	`end`
	`end`
	`end`
	`*/`
`end`	`end`
`else begin`	`else begin`
`VGA_R[0] <= 0;`	`VGA_R[0] <= 0;`
`VGA_G[0] <= 0;`	`VGA_G[0] <= 0;`
`VGA_B[0] <= 0;`	`VGA_B[0] <= 0;`
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`VGA_B[2] <= 0;`	`VGA_B[2] <= 0;`
`VGA_R[3] <= 0;`	`VGA_R[3] <= 0;`
`VGA_G[3] <= 0;`	`VGA_G[3] <= 0;`
`VGA_B[3] <= 0;`	`VGA_B[3] <= 0;`
`end`	`end`

`end`	`end`

`assign vidon = (hc < 640 && vc < 480) ? 1 : 0;`	`assign vidon = (hc < 640 && vc < 480) ? 1 : 0;`

`endmodule`	`endmodule`

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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [vga_controller.v] - Diff between revs 224 and 225