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set SVNPATH /home/nscad/samuel/Desktop/svn_atari/trunk/
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set SVNPATH /home/nscad/samuel/Desktop/svn_atari/trunk/
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set FILE_LIST {t6507lp_io.v t6507lp.v t6507lp_alu.v t6507lp_fsm.v}
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set FILE_LIST {t6507lp_io.v t6507lp.v t6507lp_alu.v t6507lp_fsm.v}
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set_attr lp_insert_clock_gating true /
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set_attr lp_insert_clock_gating true /
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set_attribute lp_insert_operand_isolation true /
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set_attr lp_insert_operand_isolation true /
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#set_attr dft_scan_style muxed_scan /
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set_attr dft_scan_style muxed_scan /
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#set_attr dft_scan_map_mode tdrc_pass /
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set_attribute hdl_search_path $SVNPATH/rtl/verilog/
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# this will force the mapping of all registers that passed dft rules into scannable registers
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set_attr lib_search_path $SVNPATH/syn/cadence/libs/
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set_attr hdl_search_path $SVNPATH/rtl/verilog/
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set_attr lib_search_path "$SVNPATH/syn/cadence/libs/ /home"
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read_hdl $FILE_LIST -v2001
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read_hdl $FILE_LIST -v2001
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set_attr library {D_CELLSL_3_3V.lib IO_CELLS_33.lib}
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set_attr library {D_CELLSL_3_3V.lib IO_CELLS_33.lib}
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set_attribute avoid false [find / -libcell LGC*]
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set_attribute avoid false [find / -libcell LGC*]
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set_attribute avoid false [find / -libcell LSG*]
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set_attribute avoid false [find / -libcell LSG*]
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set_attribute avoid false [find / -libcell LSOGC*]
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set_attribute avoid false [find / -libcell LSOGC*]
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#set_attribute avoid true [find / -libcell EN2LX1]
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set_attribute avoid true [find / -libcell EN2LX1]
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# the EN2LX1 cell always reports violations. i have also declared the dont use attribute of the cell in the .lib file
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# the EN2LX1 cell always reports violations. i have also declared the dont use attribute of the cell in the .lib file
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set_attribute lef_library {xc06_m3_FE.lef D_CELLSL.lef IO_CELLS.lef}
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set_attribute lef_library {xc06_m3_FE.lef D_CELLSL.lef IO_CELLS.lef}
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set_attr cap_table_file xc06m3_typ.CapTbl
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set_attr cap_table_file xc06m3_typ.CapTbl
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set_attr interconnect_mode ple /
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set_attr interconnect_mode ple /
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elaborate
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elaborate
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define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp_io] -port clk]
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define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp_io] -port clk]
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set_attribute slew {0 0 1 1} [find / -clock 1MHz]
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set_attribute slew {0 0 1 1} [find / -clock 1MHz]
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external_delay -clock [find / -clock 1MHz] -output 100 [all_outputs]
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external_delay -clock [find / -clock 1MHz] -output 100 [all_outputs]
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external_delay -clock [find / -clock 1MHz] -input 100 [all_inputs]
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external_delay -clock [find / -clock 1MHz] -input 100 [all_inputs]
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#0.1 ns each
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#0.1 ns each
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read_vcd simvision.vcd -module t6507lp
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define_dft shift_enable -active high [find / -port scan_enable] -name SE
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set_attribute lp_clock_gating_test_signal SE /des*/*
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#check_design
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#read_vcd simvision.vcd -module t6507lp -static
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#argh
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#check_design -all
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report timing -lint
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#report timing -lint
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check_dft_rules
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synthesize -to_generic -effort high
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synthesize -to_generic -effort high
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synthesize -to_mapped -effort high -no_incremental
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synthesize -to_mapped -effort high -no_incremental
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clock_gating share
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#clock_gating share
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define_dft scan_chain -name chain1 -sdi [find / -pin data_in[0]] -sdo [find / -pin data_out[0]] -shared_out -shared_select SE -shift_enable SE
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connect_scan_chains
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check_dft_rules
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synthesize -incremental -effort high
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synthesize -incremental -effort high
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#write_hdl t6507lp_io > gates.v
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io t6507lp_io
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write_encounter design -basename /home/nscad/samuel/Desktop/svn_atari/trunk/syn/cadence/results/t6507lp_io t6507lp_io
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