//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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//
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//
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// UART2BUS VERIFICATION
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// UART2BUS VERIFICATION
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//
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//
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// CREATOR : HANY SALAH
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// CREATOR : HANY SALAH
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// PROJECT : UART2BUS UVM TEST BENCH
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// PROJECT : UART2BUS UVM TEST BENCH
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// UNIT : AGENT
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// UNIT : AGENT
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// TITLE : UART Coverage
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// TITLE : UART Coverage
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// DESCRIPTION: THIS BLOCK INCLUDES ALL THE COVERPINS THAT ARE SAMPLED EACH STIMULUS
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// DESCRIPTION: THIS BLOCK INCLUDES ALL THE COVERPINS THAT ARE SAMPLED EACH STIMULUS
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// LOG DETAILS
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// LOG DETAILS
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//-------------
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//-------------
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// VERSION NAME DATE DESCRIPTION
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// VERSION NAME DATE DESCRIPTION
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// 1 HANY SALAH 08022016 FILE CREATION
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// 1 HANY SALAH 08022016 FILE CREATION
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// 2 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD CODE COMMENTS
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// 2 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD CODE COMMENTS
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
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//-------------------------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------------------------
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class uart_coverage extends uvm_subscriber#(uart_transaction);
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class uart_coverage extends uvm_subscriber#(uart_transaction);
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`uvm_component_utils(uart_coverage)
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`uvm_component_utils(uart_coverage)
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uart_transaction trans,_trans;
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uart_transaction trans,_trans;
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covergroup trans_attrib;
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covergroup trans_attrib;
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communication_mode:
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communication_mode:
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coverpoint trans._mode{
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coverpoint trans._mode{
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bins valid_mode = {text,binary};
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bins valid_mode = {text,binary};
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bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
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illegal_bins invalid_mode = {wrong_mode_text,wrong_mode_bin};
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}
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}
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address:
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address:
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coverpoint trans.address;
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coverpoint trans.address;
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false_data:
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coverpoint trans.false_data_en;
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unknown_prefix:
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coverpoint trans.wrong_prefix;
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endgroup:trans_attrib
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endgroup:trans_attrib
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covergroup text_mode_cov;
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covergroup text_mode_cov;
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command:
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command:
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coverpoint trans._command{
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coverpoint trans._command{
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bins valid_command ={read,2};
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bins valid_command ={read,2};
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illegal_bins invalid_command={nop,invalid_read,invalid_write};
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illegal_bins invalid_command={nop,invalid_read,invalid_write};
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}
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}
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first_white_space_field:
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first_white_space_field:
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coverpoint trans._spacetype1;
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coverpoint trans._spacetype1{bins validspace ={single,tab};
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illegal_bins invalidspace ={wrong_space};}
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second_white_space_field:
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second_white_space_field:
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coverpoint trans._spacetype2;
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coverpoint trans._spacetype2{bins validspace ={single,tab};
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illegal_bins invalidspace ={wrong_space};}
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end_of_line_field:
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end_of_line_field:
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coverpoint trans._eoltype;
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coverpoint trans._eoltype{bins valideol={cr,lf};
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illegal_bins eol ={wrong_eol};}
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prefix_character_type:
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prefix_character_type:
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coverpoint trans._chartype;
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coverpoint trans._chartype;
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endgroup:text_mode_cov
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endgroup:text_mode_cov
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covergroup binary_mode_cov;
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covergroup binary_mode_cov;
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command:
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command:
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coverpoint trans._command{
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coverpoint trans._command{
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bins normal_command={read,2,nop};
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bins normal_command={read,2,nop};
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bins wrong_command ={invalid_read,invalid_write};
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illegal_bins wrong_command ={invalid_read,invalid_write};
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}
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}
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acknowledge_requirement:
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acknowledge_requirement:
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coverpoint trans._reqack;
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coverpoint trans._reqack;
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incremental_address_requirement:
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incremental_address_requirement:
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coverpoint trans._reqinc;
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coverpoint trans._reqinc;
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Length_of_data:
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Length_of_data:
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coverpoint trans.length_data{
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coverpoint trans.length_data{
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bins zero = {0};
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bins zero = {0};
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bins valid = {[1:256]};
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bins valid = {[1:256]};
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illegal_bins invalid= {[257:$]};
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illegal_bins invalid= {[257:$]};
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}
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}
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endgroup:binary_mode_cov
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endgroup:binary_mode_cov
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function new (string name, uvm_component parent);
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function new (string name, uvm_component parent);
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super.new(name,parent);
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super.new(name,parent);
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trans_attrib = new();
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trans_attrib = new();
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text_mode_cov = new();
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text_mode_cov = new();
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binary_mode_cov = new();
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binary_mode_cov = new();
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endfunction:new
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endfunction:new
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extern function void build_phase(uvm_phase phase);
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extern function void build_phase(uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern function void connect_phase (uvm_phase phase);
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extern task run_phase (uvm_phase);
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extern task run_phase (uvm_phase);
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extern function void write (uart_transaction t);
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extern function void write (uart_transaction t);
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endclass:uart_coverage
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endclass:uart_coverage
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function void uart_coverage::build_phase (uvm_phase phase);
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function void uart_coverage::build_phase (uvm_phase phase);
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super.build_phase(phase);
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super.build_phase(phase);
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trans = uart_transaction::type_id::create("trans");
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trans = uart_transaction::type_id::create("trans");
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_trans = uart_transaction::type_id::create("_trans");
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_trans = uart_transaction::type_id::create("_trans");
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endfunction:build_phase
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endfunction:build_phase
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function void uart_coverage::connect_phase(uvm_phase phase);
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function void uart_coverage::connect_phase(uvm_phase phase);
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// cov_mon.connect(mon_fifo.analysis_export);
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endfunction:connect_phase
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endfunction:connect_phase
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task uart_coverage::run_phase(uvm_phase phase);
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task uart_coverage::run_phase(uvm_phase phase);
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endtask:run_phase
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endtask:run_phase
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function void uart_coverage::write(uart_transaction t);
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function void uart_coverage::write(uart_transaction t);
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$cast(trans,t.clone());
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$cast(trans,t.clone());
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trans_attrib.sample();
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trans_attrib.sample();
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uvm_resource_db#(int)::write_by_name("coverage_cloud","general_coverage",trans_attrib.get_coverage());
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if(trans._mode == text)
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if(trans._mode == text)
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begin
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begin
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text_mode_cov.sample();
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text_mode_cov.sample();
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uvm_resource_db#(int)::write_by_name("coverage_cloud","text_coverage",text_mode_cov.get_coverage());
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uvm_resource_db#(int)::write_by_name("coverage_cloud","text_coverage",text_mode_cov.get_coverage());
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end
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end
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else if (trans._mode == binary)
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else if (trans._mode == binary)
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begin
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begin
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binary_mode_cov.sample();
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binary_mode_cov.sample();
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uvm_resource_db#(int)::write_by_name("coverage_cloud","binary_coverage",binary_mode_cov.get_coverage());
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end
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end
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endfunction // write
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endfunction // write
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