URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [trunk/] [tb/] [run_script_packeduvm.sh] - Diff between revs 17 and 18

Rev 17	Rev 18
Line 40...	Line 40...
`#------------------------------`	`#------------------------------`
`vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl +incdir+uvm_src/ +define+UVM_1p2`	`vlog -novopt uart_top.sv +incdir+../../rtl/i2c/ +incdir+./ +incdir+../rtl +incdir+uvm_src/ +define+UVM_1p2`
`#-----------------------------`	`#-----------------------------`
`# UART Top Testbench Simulation`	`# UART Top Testbench Simulation`
`#------------------------------`	`#------------------------------`
`vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64`	`#vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64`
	`vsim -novopt +coverage -c uart_top_tb -sv_lib $UVM_HOME/lib/uvm_dpi64 -do "run -a;"`
`#run -all`	`#run -all`

`No newline at end of file`	`No newline at end of file`