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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright 2007 Ken Campbell
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-- Copyright 2011 Ken Campbell
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- $Author: sckoarn $
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-- $Author: sckoarn $
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--
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--
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-- $Date: 2008-02-24 01:34:11 $
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-- $Date: $
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--
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--
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-- $Name: not supported by cvs2svn $
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-- $Id: $
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--
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--
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-- $Id: template_tb_bhv.vhd,v 1.4 2008-02-24 01:34:11 sckoarn Exp $
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-- $Source: $
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--
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-- $Source: /home/marcus/revision_ctrl_test/oc_cvs/cvs/vhld_tb/source/template_tb_bhv.vhd,v $
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--
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--
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-- Description : The the testbench package template behave file.
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-- Description : The the testbench package template behave file.
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-- Initial GNU release.
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-- GNU release 2 Beta.
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--
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--
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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--This file is part of The VHDL Test Bench.
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--This file is part of The VHDL Test Bench.
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--
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--
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-- The VHDL Test Bench is free software; you can redistribute it and/or modify
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-- The VHDL Test Bench is free software; you can redistribute it and/or modify
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with The VHDL Test Bench; if not, write to the Free Software
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-- along with The VHDL Test Bench; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Revision History:
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2007/11/14 02:35:56 sckoarn
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-- Fix to WHILE instruction: Change if_state typo to wh_state
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--
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-- Revision 1.2 2007/09/02 04:04:04 sckoarn
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-- Update of version 1.2 tb_pkg
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-- See documentation for details
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--
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-- Revision 1.1.1.1 2007/04/06 04:06:48 sckoarn
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-- Import of the vhld_tb
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--
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--
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-------------------------------------------------------------------------------
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architecture bhv of tb_Top is
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architecture bhv of tb_Top is
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signal tb_clk : std_logic;
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signal tb_clk : std_logic;
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-- Stimulus file instruction definition
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-- Stimulus file instruction definition
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-- This is where the instructions used in the stimulus file are defined.
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-- This is where the instructions used in the stimulus file are defined.
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-- Syntax is
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-- Syntax is
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-- define_instruction(inst_def_ptr, instruction, paramiters)
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-- define_instruction(inst_def_ptr, instruction, paramiters)
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-- inst_def_ptr: is a record pointer defined in tb_pkg_header
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-- inst_def_ptr: is a record pointer defined in tb_pkg_header
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-- instruction: the text instruction name ie. "DEFINE_VAR"
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-- instruction: the text instruction name ie. "ADD_VAR"
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-- paramiters: the number of fields or paramiters passed
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-- paramiters: the number of fields or paramiters passed
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--
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--
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-- Some basic instruction are created here, the user should create new
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-- Some basic instruction are created here, the user should create new
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-- instructions below the standard ones.
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-- instructions below the standard ones.
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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define_instruction(inst_list, "END_WHILE", 0);
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define_instruction(inst_list, "END_WHILE", 0);
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define_instruction(inst_list, "MESSAGES_OFF", 0);
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define_instruction(inst_list, "MESSAGES_OFF", 0);
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define_instruction(inst_list, "MESSAGES_ON", 0);
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define_instruction(inst_list, "MESSAGES_ON", 0);
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define_instruction(inst_list, "ABORT", 0); -- Error exit from sim
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define_instruction(inst_list, "ABORT", 0); -- Error exit from sim
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define_instruction(inst_list, "FINISH", 0); -- Normal exit from sim
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define_instruction(inst_list, "FINISH", 0); -- Normal exit from sim
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define_instruction(inst_list, "INCLUDE", 1); -- Define a Variable
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define_instruction(inst_list, "INCLUDE", 1); -- Include a script file
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-- Start User defined instructions
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-- User defined instructions
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-- End User defined instructions
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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-- Read, test, and load the stimulus file
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-- Read, test, and load the stimulus file
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read_instruction_file(stimulus_file, inst_list, defined_vars, inst_sequ,
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read_instruction_file(stimulus_file, inst_list, defined_vars, inst_sequ,
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file_list);
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file_list);
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end process Read_file;
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end process Read_file;
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end bhv;
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end bhv;
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-------------------------------------------------------------------------------
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-- Revision History:
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-- version 1.4
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-- $Log: not supported by cvs2svn $
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-- Revision 1.3 2007/11/14 02:35:56 sckoarn
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|
-- Fix to WHILE instruction: Change if_state typo to wh_state
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--
|
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-- Revision 1.2 2007/09/02 04:04:04 sckoarn
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|
-- Update of version 1.2 tb_pkg
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|
-- See documentation for details
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--
|
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-- Revision 1.1.1.1 2007/04/06 04:06:48 sckoarn
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-- Import of the vhld_tb
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--
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--
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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