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[/] [xilinx_virtex_fp_library/] [trunk/] [DualPathFPAdderMappedConversions/] [rounding.v] - Diff between revs 11 and 19

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`timescale 1ns / 1ps
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Company:     UPT
// Engineer: 
// Engineer:    Constantina-Elena Gavriliu
// 
// 
// Create Date:    16:09:49 11/04/2013 
// Create Date:    16:09:49 11/04/2013 
// Design Name: 
// Design Name: 
// Module Name:    rounding 
// Module Name:    rounding 
// Project Name: 
// Project Name: 
// Target Devices: 
// Target Devices: 
// Tool versions: 
// Tool versions: 
// Description: A  B
// Description: A  B rounding
//
//
// Dependencies: 
// Dependencies: 
//
//
// Revision: 
// Revision: 
// Revision 0.01 - File Created
// Revision 0.01 - File Created
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module rounding #(      parameter SIZE_MOST_S_MANTISSA = 24,
module rounding #(      parameter SIZE_MOST_S_MANTISSA = 24,
                                        parameter SIZE_LEAST_S_MANTISSA= 25)
                                        parameter SIZE_LEAST_S_MANTISSA= 25)
                                (       input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
                                (       input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
                                        input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
                                        input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
 
                                        input correction,
                                        output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
                                        output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
 
 
        wire g, sticky, round_dec;
        wire g, sticky, round_dec;
 
 
        assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
        assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
        assign sticky = |(dummy_bits[SIZE_LEAST_S_MANTISSA - 2 : 0]);
        assign sticky   = (|(dummy_bits[SIZE_LEAST_S_MANTISSA - 3 : 0]));
        assign round_dec = g & (unrounded_mantissa[0] | sticky);
        assign round    = dummy_bits[SIZE_LEAST_S_MANTISSA - 2];
        assign rounded_mantissa = unrounded_mantissa + round_dec;
 
 
        assign round_dec                = g & (unrounded_mantissa[0] | sticky | round);
 
        assign rounded_mantissa = correction? (round_dec? unrounded_mantissa : unrounded_mantissa - 1'b1) : (round_dec? unrounded_mantissa + 1 : unrounded_mantissa);
 
 
endmodule
endmodule
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