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https://opencores.org/ocsvn/xilinx_virtex_fp_library/xilinx_virtex_fp_library/trunk
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Rev 19 |
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Company: UPT
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// Engineer:
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// Engineer: Constantina-Elena Gavriliu
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//
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//
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// Create Date: 18:00:33 10/15/2013
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// Create Date: 18:00:33 10/15/2013
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// Design Name:
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// Design Name:
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// Module Name: shifter
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// Module Name: shifter
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// Project Name:
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// Project Name:
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// Target Devices:
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// Target Devices:
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// Tool versions:
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// Tool versions:
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// Description:
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// Description:
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//
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//
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// Dependencies:
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// Dependencies: d_ff.v
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//
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//
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// Revision:
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// Revision:
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// Revision 0.01 - File Created
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// Revision 0.01 - File Created
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// Additional Comments:
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// Additional Comments:
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//
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//
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genvar i;
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genvar i;
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for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
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for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
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begin : BARREL_SHIFTER_GENERATION
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begin : BARREL_SHIFTER_GENERATION
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if (DIRECTION == 1)
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if (DIRECTION == 1)
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begin : LEFT
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begin : LEFT
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//begin : 1st_check
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genvar j;
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genvar j;
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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begin : MUX_GEN_L
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begin : MUX_GEN_L
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if (j < 2 ** i)
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if (j < 2 ** i)
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begin : ZERO_INS_L
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begin : ZERO_INS_L
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Line 58... |
if (j >= 2 ** i)
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if (j >= 2 ** i)
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begin : BIT_INS_L
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begin : BIT_INS_L
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
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end
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end
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end
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end
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//end
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end
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end
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if (DIRECTION == 0)
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if (DIRECTION == 0)
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begin : RIGHT
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begin : RIGHT
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//begin : 2nd_check
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genvar j;
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genvar j;
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
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begin : MUX_GEN_R
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begin : MUX_GEN_R
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if (OUTPUT_SIZE - 1 < 2 ** i + j)
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if (OUTPUT_SIZE - 1 < 2 ** i + j)
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begin : ZERO_INS_R
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begin : ZERO_INS_R
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Line 75... |
if (OUTPUT_SIZE - 1 >= 2 ** i + j)
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if (OUTPUT_SIZE - 1 >= 2 ** i + j)
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begin : BIT_INS_R
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begin : BIT_INS_R
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
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assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
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end
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end
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end
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end
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//end
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end
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end
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if (PIPELINE != 0)
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if (PIPELINE != 0)
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begin : PIPELINE_INSERTION
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begin : PIPELINE_INSERTION
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if (POSITION[i] == 1'b1)
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if (POSITION[i] == 1'b1)
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