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Subversion Repositories xilinx_virtex_fp_library

[/] [xilinx_virtex_fp_library/] [trunk/] [GeneralPrecMAF/] [leading_zeros.v] - Diff between revs 3 and 5

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Rev 3 Rev 5
Line 63... Line 63... 
        generate
 
        generate
 
                begin : level_generation_begin
 
                begin : level_generation_begin
 
                        genvar i;
 
                        genvar i;
 
                        for (i = 1; i <= nr_levels - 1; i = i + 1)
 
                        for (i = 1; i <= nr_levels - 1; i = i + 1)
 
                        begin : level_generation
 
                        begin : level_generation
 
                                //begin : v_levels_begin
 
 
 
                                        genvar j;
 
                                        genvar j;
 
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
 
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
 
                                        begin : v_levels
 
                                        begin : v_levels
 
                                                assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
 
                                                assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
 
                                        end
 
                                        end
 
                                //end
 
 
 
 
 
 
 
                                //begin : p_levels_begin
 
 
 
                                //      genvar j;
 
 
 
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
 
                                        for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
 
                                        begin : p_levels
 
                                        begin : p_levels
 
                                                assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
 
                                                assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
 
                                                assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
 
                                                assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
 
                                        end
 
                                        end
 
                                //end
 
 
 
                        end
 
                        end
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
        generate
 
        generate
 
                if (PIPELINE != 0)
 
                if (PIPELINE != 0)
 
                begin : pipeline_stages
 
                begin : pipeline_stages
 
                        //begin : INSERTION_begin
 
 
 
                                genvar i;
 
                                genvar i;
 
                                for (i = 0; i <= nr_levels - 2; i = i + 1)
 
                                for (i = 0; i <= nr_levels - 2; i = i + 1)
 
                                begin : INSERTION
 
                                begin : INSERTION
 
                                        if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
 
                                        if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
 
                                        begin : INS
 
                                        begin : INS
Line 102... Line 96... 
                                        begin : NO_INS
 
                                        begin : NO_INS
 
                                                assign p_q[i] = p_d[i];
 
                                                assign p_q[i] = p_d[i];
 
                                                assign v_q[i] = v_d[i];
 
                                                assign v_q[i] = v_d[i];
 
                                        end
 
                                        end
 
                                end
 
                                end
 
                        //end
 
 
 
                        assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
 
                        assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
 
                        assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
 
                        assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
        generate
 
        generate
 
                if (PIPELINE == 0)
 
                if (PIPELINE == 0)
 
                begin : no_pipeline
 
                begin : no_pipeline
 
                        //begin : xhdl4
 
 
 
                                genvar i;
 
                                genvar i;
 
                                for (i = 0; i <= nr_levels - 1; i = i + 1)
 
                                for (i = 0; i <= nr_levels - 1; i = i + 1)
 
                                begin : NO_INSERTION
 
                                begin : NO_INSERTION
 
                                        assign p_q[i] = p_d[i];
 
                                        assign p_q[i] = p_d[i];
 
                                        assign v_q[i] = v_d[i];
 
                                        assign v_q[i] = v_d[i];
 
                                end
 
                                end
 
                        //end
 
 
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
        assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
 
        assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
 
 
 
 
Line 134... Line 126... 
                                assign lz[i] = lzc[i] & ((~ovf));
 
                                assign lz[i] = lzc[i] & ((~ovf));
 
                        end
 
                        end
 
                end
 
                end
 
        endgenerate
 
        endgenerate
 
 
 
 
 
        //assign a_out = (a_complete[max_pow_2 - 1: max_pow_2 - SIZE_INT])<<lzc;
 
 
 
        //output [SIZE_INT-1:0]   a_out;
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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