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[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [clock.veo] - Rev 15
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//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____10.000______0.000______50.0_____1200.000____150.000
// CLK_OUT2____50.000______0.000______50.0______200.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
clock instance_name
(// Clock in ports
.CLK_IN1(CLK_IN1), // IN
// Clock out ports
.CLK_OUT1(CLK_OUT1), // OUT
.CLK_OUT2(CLK_OUT2), // OUT
// Status and control signals
.LOCKED(LOCKED)); // OUT
// INST_TAG_END ------ End INSTANTIATION Template ---------
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