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https://opencores.org/ocsvn/a-z80/a-z80/trunk
Subversion Repositories a-z80
[/] [a-z80/] [trunk/] [host/] [basic_nexys3/] [ipcore_dir/] [coregen.cgp] - Rev 15
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
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