Subversion Repositories aes-128_pipelined_encryption

Release 12.1 - xst M.53d (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.15 secs
 
--> Reading design: Top_PipelinedCipher.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "Top_PipelinedCipher.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "Top_PipelinedCipher"
Output Format                      : NGC
Target Device                      : xc6vcx240t-2-ff784

---- Source Options
Top Module Name                    : Top_PipelinedCipher
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : auto
Reduce Control Sets                : auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 32
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Library Search Order               : Top_PipelinedCipher.lso
Keep Hierarchy                     : NO
Netlist Hierarchy                  : as_optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing Verilog file "E:\AES\AES\SBox.v" into library work
Parsing module <SBox>.
Parsing Verilog file "E:\AES\AES\SubBytes.v" into library work
Parsing module <SubBytes>.
Parsing Verilog file "E:\AES\AES\ShiftRows.v" into library work
Parsing module <ShiftRows>.
Parsing Verilog file "E:\AES\AES\RoundKeyGen.v" into library work
Parsing module <RoundKeyGen>.
Parsing Verilog file "E:\AES\AES\MixColumns.v" into library work
Parsing module <MixColumns>.
Parsing Verilog file "E:\AES\AES\AddRoundKey.v" into library work
Parsing module <AddRoundKey>.
Parsing Verilog file "E:\AES\AES\Round.v" into library work
Parsing module <Round>.
Parsing Verilog file "E:\AES\AES\KeyExpantion.v" into library work
Parsing module <KeyExpantion>.
Parsing Verilog file "E:\AES\AES\Top_PipelinedCipher.v" into library work
Parsing module <Top_PipelinedCipher>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <Top_PipelinedCipher>.

Elaborating module <KeyExpantion(DATA_W=128,KEY_L=128,NO_ROUNDS=10)>.

Elaborating module <RoundKeyGen(KEY_L=128)>.

Elaborating module <SubBytes(DATA_W=32)>.

Elaborating module <SBox>.

Elaborating module <AddRoundKey(DATA_W=128)>.

Elaborating module <Round(DATA_W=128)>.

Elaborating module <SubBytes(DATA_W=128)>.

Elaborating module <ShiftRows(DATA_W=128)>.

Elaborating module <MixColumns(DATA_W=128)>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <Top_PipelinedCipher>.
    Related source file is "e:/aes/aes/top_pipelinedcipher.v".
        DATA_W = 128
        KEY_L = 128
        NO_ROUNDS = 10
    Found 128-bit register for signal <data_shift2key_delayed>.
    Found 1-bit register for signal <valid_shift2key_delayed>.
    Summary:
        inferred 129 D-type flip-flop(s).
Unit <Top_PipelinedCipher> synthesized.

Synthesizing Unit <KeyExpantion>.
    Related source file is "e:/aes/aes/keyexpantion.v".
        DATA_W = 128
        KEY_L = 128
        NO_ROUNDS = 10
    Summary:
        no macro.
Unit <KeyExpantion> synthesized.

Synthesizing Unit <RoundKeyGen>.
    Related source file is "e:/aes/aes/roundkeygen.v".
        KEY_L = 128
        WORD = 32
    Found 128-bit register for signal <Key_FirstStage>.
    Found 128-bit register for signal <Key_SecondStage>.
    Found 128-bit register for signal <round_key_delayed>.
    Found 128-bit register for signal <round_key>.
    Found 1-bit register for signal <valid_round_key>.
    Found 1-bit register for signal <valid_out>.
    Found 1-bit register for signal <valid_FirstStage>.
    Summary:
        inferred 515 D-type flip-flop(s).
Unit <RoundKeyGen> synthesized.

Synthesizing Unit <SubBytes_1>.
    Related source file is "e:/aes/aes/subbytes.v".
        DATA_W = 32
        NO_BYTES = 4
    Found 1-bit register for signal <valid_out>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <SubBytes_1> synthesized.

Synthesizing Unit <SBox>.
    Related source file is "e:/aes/aes/sbox.v".
    Found 8-bit register for signal <dout>.
    Found 256x8-bit Read Only RAM for signal <addr[7]_GND_5_o_wide_mux_0_OUT>
    Summary:
        inferred   1 RAM(s).
        inferred   8 D-type flip-flop(s).
Unit <SBox> synthesized.

Synthesizing Unit <AddRoundKey>.
    Related source file is "e:/aes/aes/addroundkey.v".
        DATA_W = 128
    Found 128-bit register for signal <data_out>.
    Found 1-bit register for signal <valid_out>.
    Summary:
        inferred 129 D-type flip-flop(s).
Unit <AddRoundKey> synthesized.

Synthesizing Unit <Round>.
    Related source file is "e:/aes/aes/round.v".
        DATA_W = 128
    Summary:
        no macro.
Unit <Round> synthesized.

Synthesizing Unit <SubBytes_2>.
    Related source file is "e:/aes/aes/subbytes.v".
        DATA_W = 128
        NO_BYTES = 16
    Found 1-bit register for signal <valid_out>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <SubBytes_2> synthesized.

Synthesizing Unit <ShiftRows>.
    Related source file is "e:/aes/aes/shiftrows.v".
        DATA_W = 128
    Found 128-bit register for signal <data_out>.
    Found 1-bit register for signal <valid_out>.
    Summary:
        inferred 129 D-type flip-flop(s).
Unit <ShiftRows> synthesized.

Synthesizing Unit <MixColumns>.
    Related source file is "e:/aes/aes/mixcolumns.v".
        DATA_W = 128
    Found 128-bit register for signal <data_out>.
    Found 1-bit register for signal <valid_out>.
    Summary:
        inferred 129 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <MixColumns> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 200
 256x8-bit single-port Read Only RAM                   : 200
# Registers                                            : 352
 1-bit register                                        : 81
 128-bit register                                      : 71
 8-bit register                                        : 200
# Multiplexers                                         : 144
 8-bit 2-to-1 multiplexer                              : 144
# Xors                                                 : 349
 128-bit xor2                                          : 11
 32-bit xor2                                           : 50
 8-bit xor2                                            : 144
 8-bit xor5                                            : 144

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <SBox>.
INFO:Xst:3030 - HDL ADVISOR - Register <dout> currently described with an asynchronous reset, could be combined with distributed RAM <Mram_addr[7]_GND_5_o_wide_mux_0_OUT> for implementation on block RAM resources if you made this reset synchronous instead.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 8-bit                    |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_addr[7]_GND_5_o_wide_mux_0_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Unit <SBox> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 200
 256x8-bit single-port distributed Read Only RAM       : 200
# Registers                                            : 10769
 Flip-Flops                                            : 10769
# Multiplexers                                         : 144
 8-bit 2-to-1 multiplexer                              : 144
# Xors                                                 : 349
 128-bit xor2                                          : 11
 32-bit xor2                                           : 50
 8-bit xor2                                            : 144
 8-bit xor5                                            : 144

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <Top_PipelinedCipher> ...

Optimizing unit <KeyExpantion> ...

Optimizing unit <RoundKeyGen> ...

Optimizing unit <SBox> ...

Optimizing unit <AddRoundKey> ...

Optimizing unit <SubBytes_2> ...

Optimizing unit <MixColumns> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Top_PipelinedCipher, actual ratio is 12.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 10769
 Flip-Flops                                            : 10769

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : Top_PipelinedCipher.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 15403
#      INV                         : 1
#      LUT2                        : 810
#      LUT3                        : 320
#      LUT4                        : 1600
#      LUT5                        : 1040
#      LUT6                        : 6832
#      MUXF7                       : 3200
#      MUXF8                       : 1600
# FlipFlops/Latches                : 10769
#      FDC                         : 81
#      FDCE                        : 10688
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 388
#      IBUF                        : 259
#      OBUF                        : 129

Device utilization summary:
---------------------------

Selected Device : 6vcx240tff784-2 


Slice Logic Utilization: 
 Number of Slice Registers:           10769  out of  301440     3%  
 Number of Slice LUTs:                10603  out of  150720     7%  
    Number used as Logic:             10603  out of  150720     7%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:  15921
   Number with an unused Flip Flop:    5152  out of  15921    32%  
   Number with an unused LUT:          5318  out of  15921    33%  
   Number of fully used LUT-FF pairs:  5451  out of  15921    34%  
   Number of unique control sets:        82

IO Utilization: 
 Number of IOs:                         389
 Number of bonded IOBs:                 389  out of    400    97%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     32     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 10769 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 1.564ns (Maximum Frequency: 639.391MHz)
   Minimum input arrival time before clock: 1.252ns
   Maximum output required time after clock: 0.664ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 1.564ns (frequency: 639.391MHz)
  Total number of paths / destination ports: 75065 / 20943
-------------------------------------------------------------------------
Delay:               1.564ns (Levels of Logic = 3)
  Source:            U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (FF)
  Destination:       U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 to U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            33   0.317   0.826  U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (U_KEYEXP/RKGEN_U0/Key_FirstStage_24)
     LUT6:I0->O            1   0.061   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23)
     MUXF7:I1->O           1   0.211   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f7_0 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f71)
     MUXF8:I0->O           1   0.149   0.000  U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f8 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/addr[7]_GND_5_o_wide_mux_0_OUT<1>)
     FDCE:D                   -0.002          U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_1
    ----------------------------------------
    Total                      1.564ns (0.738ns logic, 0.826ns route)
                                       (47.2% logic, 52.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 771 / 514
-------------------------------------------------------------------------
Offset:              1.252ns (Levels of Logic = 2)
  Source:            cipherkey_valid_in (PAD)
  Destination:       U0_ARK/data_out_127 (FF)
  Destination Clock: clk rising

  Data Path: cipherkey_valid_in to U0_ARK/data_out_127
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           130   0.003   0.505  cipherkey_valid_in_IBUF (cipherkey_valid_in_IBUF)
     LUT2:I1->O          129   0.061   0.487  U0_ARK/data_valid_in_key_valid_in_AND_2_o1 (U0_ARK/data_valid_in_key_valid_in_AND_2_o)
     FDCE:CE                   0.196          U0_ARK/data_out_0
    ----------------------------------------
    Total                      1.252ns (0.260ns logic, 0.992ns route)
                                       (20.8% logic, 79.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 129 / 129
-------------------------------------------------------------------------
Offset:              0.664ns (Levels of Logic = 1)
  Source:            U_KEY/data_out_127 (FF)
  Destination:       cipher_text<127> (PAD)
  Source Clock:      clk rising

  Data Path: U_KEY/data_out_127 to cipher_text<127>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.317   0.344  U_KEY/data_out_127 (U_KEY/data_out_127)
     OBUF:I->O                 0.003          cipher_text_127_OBUF (cipher_text<127>)
    ----------------------------------------
    Total                      0.664ns (0.320ns logic, 0.344ns route)
                                       (48.2% logic, 51.8% route)

=========================================================================


Total REAL time to Xst completion: 106.00 secs
Total CPU time to Xst completion: 105.60 secs
 
--> 

Total memory usage is 397192 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)