Subversion Repositories aes-128_pipelined_encryption

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Release 12.1 Trace  (nt64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

E:\ISE12\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3
-fastpaths -xml Top_PipelinedCipher.twx Top_PipelinedCipher.ncd -o
Top_PipelinedCipher.twr Top_PipelinedCipher.pcf -ucf Top_PipelinedCipher.ucf

Design file:              Top_PipelinedCipher.ncd
Physical constraint file: Top_PipelinedCipher.pcf
Device,package,speed:     xc6vcx240t,ff784,C,-2 (PRELIMINARY 1.04 2010-04-09)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;

 75065 paths analyzed, 74633 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   4.952ns.
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Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 (SLICE_X40Y71.CE), 1 path
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Slack (setup path):     0.048ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U0_ARK/valid_out (FF)
  Destination:          ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.893ns (Levels of Logic = 0)
  Clock Path Skew:      -0.024ns (1.569 - 1.593)
  Source Clock:         clk_BUFGP rising at 0.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y140.AQ     Tcko                  0.337   U0_ARK/valid_out
                                                       U0_ARK/valid_out
    SLICE_X40Y71.CE      net (fanout=129)      4.272   U0_ARK/valid_out
    SLICE_X40Y71.CLK     Tceck                 0.284   ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout<0>
                                                       ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0
    -------------------------------------------------  ---------------------------
    Total                                      4.893ns (0.621ns logic, 4.272ns route)
                                                       (12.7% logic, 87.3% route)

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Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 (SLICE_X43Y72.CE), 1 path
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Slack (setup path):     0.150ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U0_ARK/valid_out (FF)
  Destination:          ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.797ns (Levels of Logic = 0)
  Clock Path Skew:      -0.018ns (1.575 - 1.593)
  Source Clock:         clk_BUFGP rising at 0.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y140.AQ     Tcko                  0.337   U0_ARK/valid_out
                                                       U0_ARK/valid_out
    SLICE_X43Y72.CE      net (fanout=129)      4.142   U0_ARK/valid_out
    SLICE_X43Y72.CLK     Tceck                 0.318   ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout<1>
                                                       ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1
    -------------------------------------------------  ---------------------------
    Total                                      4.797ns (0.655ns logic, 4.142ns route)
                                                       (13.7% logic, 86.3% route)

--------------------------------------------------------------------------------

Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 (SLICE_X43Y76.CE), 1 path
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Slack (setup path):     0.159ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U0_ARK/valid_out (FF)
  Destination:          ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.789ns (Levels of Logic = 0)
  Clock Path Skew:      -0.017ns (1.576 - 1.593)
  Source Clock:         clk_BUFGP rising at 0.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y140.AQ     Tcko                  0.337   U0_ARK/valid_out
                                                       U0_ARK/valid_out
    SLICE_X43Y76.CE      net (fanout=129)      4.134   U0_ARK/valid_out
    SLICE_X43Y76.CLK     Tceck                 0.318   ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout<2>
                                                       ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2
    -------------------------------------------------  ---------------------------
    Total                                      4.789ns (0.655ns logic, 4.134ns route)
                                                       (13.7% logic, 86.3% route)

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Hold Paths: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 (SLICE_X60Y160.A5), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.006ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4 (FF)
  Destination:          U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.116ns (Levels of Logic = 1)
  Clock Path Skew:      0.110ns (0.784 - 0.674)
  Source Clock:         clk_BUFGP rising at 5.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4 to U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X61Y158.BQ     Tcko                  0.098   U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout<4>
                                                       U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4
    SLICE_X60Y160.A5     net (fanout=2)        0.119   U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout<4>
    SLICE_X60Y160.CLK    Tah         (-Th)     0.101   U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed<39>
                                                       U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/temp_round_key<4>1
                                                       U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4
    -------------------------------------------------  ---------------------------
    Total                                      0.116ns (-0.003ns logic, 0.119ns route)
                                                       (-2.6% logic, 102.6% route)

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Paths for end point U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 (SLICE_X40Y160.A5), 1 path
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Slack (hold path):      0.016ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12 (FF)
  Destination:          U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.124ns (Levels of Logic = 1)
  Clock Path Skew:      0.108ns (0.748 - 0.640)
  Source Clock:         clk_BUFGP rising at 5.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12 to U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X40Y159.CQ     Tcko                  0.115   U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage<14>
                                                       U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12
    SLICE_X40Y160.A5     net (fanout=1)        0.110   U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage<12>
    SLICE_X40Y160.CLK    Tah         (-Th)     0.101   U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed<47>
                                                       U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/temp_round_key<12>1
                                                       U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12
    -------------------------------------------------  ---------------------------
    Total                                      0.124ns (0.014ns logic, 0.110ns route)
                                                       (11.3% logic, 88.7% route)

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Paths for end point ROUND[8].U_ROUND/U_MIX/data_out_38 (SLICE_X54Y160.B6), 1 path
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Slack (hold path):      0.028ns (requirement - (clock path skew + uncertainty - data path))
  Source:               ROUND[8].U_ROUND/U_SH/data_out_46 (FF)
  Destination:          ROUND[8].U_ROUND/U_MIX/data_out_38 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.137ns (Levels of Logic = 1)
  Clock Path Skew:      0.109ns (0.773 - 0.664)
  Source Clock:         clk_BUFGP rising at 5.000ns
  Destination Clock:    clk_BUFGP rising at 5.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: ROUND[8].U_ROUND/U_SH/data_out_46 to ROUND[8].U_ROUND/U_MIX/data_out_38
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X54Y159.DQ     Tcko                  0.115   ROUND[8].U_ROUND/U_SH/data_out<46>
                                                       ROUND[8].U_ROUND/U_SH/data_out_46
    SLICE_X54Y160.B6     net (fanout=5)        0.099   ROUND[8].U_ROUND/U_SH/data_out<46>
    SLICE_X54Y160.CLK    Tah         (-Th)     0.077   ROUND[8].U_ROUND/U_MIX/data_out<40>
                                                       ROUND[8].U_ROUND/U_MIX/Mxor_State_Mulx3[8][7]_State_Mulx2[11][7]_xor_99_OUT_6_xo<0>1
                                                       ROUND[8].U_ROUND/U_MIX/data_out_38
    -------------------------------------------------  ---------------------------
    Total                                      0.137ns (0.038ns logic, 0.099ns route)
                                                       (27.7% logic, 72.3% route)

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Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 3.571ns (period - min period limit)
  Period: 5.000ns
  Min period limit: 1.429ns (699.790MHz) (Tbcper_I)
  Physical resource: clk_BUFGP/BUFG/I0
  Logical resource: clk_BUFGP/BUFG/I0
  Location pin: BUFGCTRL_X0Y0.I0
  Clock network: clk_BUFGP/IBUFG
--------------------------------------------------------------------------------
Slack: 4.168ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 0.416ns (Trpw)
  Physical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout<5>/SR
  Logical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout_5/SR
  Location pin: SLICE_X0Y81.SR
  Clock network: ROUND[0].U_ROUND/U_KEY/reset_inv_BUFG
--------------------------------------------------------------------------------
Slack: 4.168ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.000ns
  High pulse: 2.500ns
  High pulse limit: 0.416ns (Trpw)
  Physical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout<1>/SR
  Logical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout_1/SR
  Location pin: SLICE_X0Y85.SR
  Clock network: ROUND[0].U_ROUND/U_KEY/reset_inv_BUFG
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    4.952|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 75065 paths, 0 nets, and 69159 connections

Design statistics:
   Minimum period:   4.952ns{1}   (Maximum frequency: 201.939MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Wed Jul 17 15:21:24 2013 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 873 MB