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[/] [amber/] [trunk/] [doc/] [ReleaseChecklist.txt] - Rev 35

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1. Run all tests using both A23 and A25 using all cache size configurations.
2. Synthesise both a23 and a25 cores. 
   Both cores must pass timing; Spartan6 at 40MHz, Virtex6 at 80Mhz, with max caches
   Check all synthesis warnings, clean up as many as possible.

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