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[/] [amber/] [trunk/] [hw/] [tests/] [barrel_shift.S] - Rev 64
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/*****************************************************************// //// Amber 2 Core Instruction Test //// //// This file is part of the Amber project //// http://www.opencores.org/project,amber //// //// Description //// Tests lsl, ror //// //// Author(s): //// - Conor Santifort, csantifort.amber@gmail.com //// ////////////////////////////////////////////////////////////////////// //// Copyright (C) 2010 Authors and OPENCORES.ORG //// //// This source file may be used and distributed without //// restriction provided that this copyright statement is not //// removed from the file and that any derivative work contains //// the original copyright notice and the associated disclaimer. //// //// This source file is free software; you can redistribute it //// and/or modify it under the terms of the GNU Lesser General //// Public License as published by the Free Software Foundation; //// either version 2.1 of the License, or (at your option) any //// later version. //// //// This source is distributed in the hope that it will be //// useful, but WITHOUT ANY WARRANTY; without even the implied //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// PURPOSE. See the GNU Lesser General Public License for more //// details. //// //// You should have received a copy of the GNU Lesser General //// Public License along with this source; if not, download it //// from http://www.opencores.org/lgpl.shtml //// //*****************************************************************/#include "amber_registers.h"#include "amber_macros.h".section .text.globl mainmain:@ Run through the test 4 times@ 1 - cache off@ 2 - cache on but empty@ 3 - cache on and loaded@ 4 - same as 3mov r10, #4/* lsl 0 */1: mov r1, #1mov r2, r1, lsl #0expect r2, 1, __LINE__/* lsl 1 */mov r4, #1mov r5, r4, lsl #1expect r5, 2, __LINE__/* lsl 31 */mov r7, #1mov r8, r1, lsl #31expect r8, 0x80000000, __LINE__/* lsr 1 */mov r1, #2mov r2, r1, lsr #1expect r2, 1, __LINE__/* lsr 8 */mov r4, #0xff00mov r5, r4, lsr #8expect r5, 0xff, __LINE__/* ror 8 */ldr r6, Data1mov r7, r6, ror #8ldr r8, Data2compare r7, r8, __LINE__@ ---------------------@ Sequences of shift operations@ ---------------------@ lslmov r0, #0mov r1, #1mov r2, #2mov r3, #3mov r4, #4mov r5, #5mov r6, r3, lsl #31mov r7, r0, lsl #2mov r8, r1, lsl #11mov r9, r2, lsl #17expect r6, 0x80000000, __LINE__expect r7, 0x00000000, __LINE__expect r8, 0x00000800, __LINE__expect r9, 0x00040000, __LINE__mov r6, r3, lsl #30mov r7, r1, lsl #2mov r8, r2, lsl #4mov r9, r3, lsl #5expect r6, 0xc0000000, __LINE__expect r7, 0x00000004, __LINE__expect r8, 0x00000020, __LINE__expect r9, 0x00000060, __LINE__@ lsrmov r0, #0x80000000mov r1, #0x7f000000mov r2, #0x80000001mov r3, #0x7fffffffmov r4, #0x7ffffffemov r5, #0x55000000orr r5, r5, #0x55mov r6, r0, lsr #1mov r7, r0, lsr #2mov r8, r1, lsr #24mov r9, r2, lsr #1expect r6, 0x40000000, __LINE__expect r7, 0x20000000, __LINE__expect r8, 0x0000007f, __LINE__expect r9, 0x40000000, __LINE__@ ---------------------@ Enable the cache@ ---------------------mvn r0, #0mcr 15, 0, r0, cr3, cr0, 0 @ cacheable areamov r0, #1mcr 15, 0, r0, cr2, cr0, 0 @ cache enablesubs r10, r10, #1bne 1bb testpasstestfail:ldr r11, AdrTestStatusstr r10, [r11]b testfailtestpass:ldr r11, AdrTestStatusmov r10, #17str r10, [r11]b testpass/* Write 17 to this address to generate a Test Passed message */AdrTestStatus: .word ADR_AMBER_TEST_STATUSData1: .word 0x12345678Data2: .word 0x78123456/* ========================================================================= *//* ========================================================================= */
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