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[/] [amber/] [trunk/] [hw/] [vlog/] [README.txt] - Rev 32
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Missing files. These files are not provided as part of theamber package for copyright reasons. They are only neededto do simulations with real FPGA comonent models.The following files are generated by Xilinx coregenfor the DDR3 Interface in the Spartan-6 FPGA used in the SP605development board.xs6_ddr3/iodrp_controller.vxs6_ddr3/iodrp_mcb_controller.vxs6_ddr3/mcb_ddr3.vxs6_ddr3/mcb_raw_wrapper.vxs6_ddr3/mcb_soft_calibration_top.vxs6_ddr3/mcb_soft_calibration.vxs6_ddr3/memc3_infrastructure.vxs6_ddr3/memc3_wrapper.vThe following files are generated by Xilinx coregenfor the DDR3 Interface in the Virtex-6 FPGA.xv6_ddr3/arb_mux.vxv6_ddr3/arb_row_col.vxv6_ddr3/arb_select.vxv6_ddr3/bank_cntrl.vxv6_ddr3/bank_common.vxv6_ddr3/bank_compare.vxv6_ddr3/bank_mach.vxv6_ddr3/bank_queue.vxv6_ddr3/bank_state.vxv6_ddr3/circ_buffer.vxv6_ddr3/clk_ibuf.vxv6_ddr3/col_mach.vxv6_ddr3/ddr2_ddr3_chipscope.vxv6_ddr3/ecc_buf.vxv6_ddr3/ecc_dec_fix.vxv6_ddr3/ecc_gen.vxv6_ddr3/ecc_merge_enc.vxv6_ddr3/infrastructure.vxv6_ddr3/iodelay_ctrl.vxv6_ddr3/mc.vxv6_ddr3/memc_ui_top.vxv6_ddr3/mem_intfc.vxv6_ddr3/phy_ck_iob.vxv6_ddr3/phy_clock_io.vxv6_ddr3/phy_control_io.vxv6_ddr3/phy_data_io.vxv6_ddr3/phy_dly_ctrl.vxv6_ddr3/phy_dm_iob.vxv6_ddr3/phy_dq_iob.vxv6_ddr3/phy_dqs_iob.vxv6_ddr3/phy_init.vxv6_ddr3/phy_ocb_mon_top.vxv6_ddr3/phy_ocb_mon.vxv6_ddr3/phy_pd_top.vxv6_ddr3/phy_pd.vxv6_ddr3/phy_rdclk_gen.vxv6_ddr3/phy_rdctrl_sync.vxv6_ddr3/phy_rddata_sync.vxv6_ddr3/phy_rdlvl.vxv6_ddr3/phy_read.vxv6_ddr3/phy_top.vxv6_ddr3/phy_write.vxv6_ddr3/phy_wrlvl.vxv6_ddr3/rank_cntrl.vxv6_ddr3/rank_common.vxv6_ddr3/rank_mach.vxv6_ddr3/rd_bitslip.vxv6_ddr3/round_robin_arb.vxv6_ddr3/ui_cmd.vxv6_ddr3/ui_rd_data.vxv6_ddr3/ui_top.vxv6_ddr3/ui_wr_data.vxv6_ddr3/xv6_ddr3.vThe following files provide a highly accurate model of a realDDR3 memory device. They are supplied by Xilinx along witha DDR3 memory interface generated by coregen.tb/ddr3_model_c3.vtb/ddr3_model_parameters_c3.vh
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