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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN" "http://www.w3.org/TR/html4/strict.dtd"> <HTML> <HEAD> <TITLE>html/Listing_of_baudgen.vhd</TITLE> <META NAME="generator" CONTENT="HTML::TextToHTML v2.46"> <LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css"> </HEAD> <BODY> <P><table class="ttop"><th class="tpre"><a href="11_Listing_of_avr_fpga.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="13_Listing_of_common.vhd.html">Next Lesson</a></th></table> <hr> <H1><A NAME="section_1">12 LISTING OF baudgen.vhd</A></H1> <pre class="vhdl"> 1 ------------------------------------------------------------------------------- 2 -- 3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann 4 -- 5 -- This code is free software: you can redistribute it and/or modify 6 -- it under the terms of the GNU General Public License as published by 7 -- the Free Software Foundation, either version 3 of the License, or 8 -- (at your option) any later version. 9 -- 10 -- This code is distributed in the hope that it will be useful, 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 -- GNU General Public License for more details. 14 -- 15 -- You should have received a copy of the GNU General Public License 16 -- along with this code (see the file named COPYING). 17 -- If not, see http://www.gnu.org/licenses/. 18 -- 19 ------------------------------------------------------------------------------- 20 ------------------------------------------------------------------------------- 21 -- 22 -- Module Name: baudgen - Behavioral 23 -- Create Date: 13:51:24 11/07/2009 24 -- Description: fixed baud rate generator 25 -- 26 ------------------------------------------------------------------------------- 27 -- 28 library IEEE; 29 use IEEE.STD_LOGIC_1164.ALL; 30 use IEEE.STD_LOGIC_ARITH.ALL; 31 use IEEE.STD_LOGIC_UNSIGNED.ALL; 32 33 entity baudgen is 34 generic(clock_freq : std_logic_vector(31 downto 0); 35 baud_rate : std_logic_vector(27 downto 0)); 36 port( I_CLK : in std_logic; 37 38 I_CLR : in std_logic; 39 Q_CE_1 : out std_logic; -- baud x 1 clock enable 40 Q_CE_16 : out std_logic); -- baud x 16 clock enable 41 end baudgen; 42 43 44 architecture Behavioral of baudgen is 45 46 constant BAUD_16 : std_logic_vector(31 downto 0) := baud_rate & "0000"; 47 constant LIMIT : std_logic_vector(31 downto 0) := clock_freq - BAUD_16; 48 49 signal L_CE_16 : std_logic; 50 signal L_CNT_16 : std_logic_vector( 3 downto 0); 51 signal L_COUNTER : std_logic_vector(31 downto 0); 52 53 begin 54 55 baud16: process(I_CLK) 56 begin 57 if (rising_edge(I_CLK)) then 58 if (I_CLR = '1') then 59 L_COUNTER <= X"00000000"; 60 elsif (L_COUNTER >= LIMIT) then 61 L_COUNTER <= L_COUNTER - LIMIT; 62 else 63 L_COUNTER <= L_COUNTER + BAUD_16; 64 end if; 65 end if; 66 end process; 67 68 baud1: process(I_CLK) 69 begin 70 if (rising_edge(I_CLK)) then 71 if (I_CLR = '1') then 72 L_CNT_16 <= "0000"; 73 elsif (L_CE_16 = '1') then 74 L_CNT_16 <= L_CNT_16 + "0001"; 75 end if; 76 end if; 77 end process; 78 79 L_CE_16 <= '1' when (L_COUNTER >= LIMIT) else '0'; 80 Q_CE_16 <= L_CE_16; 81 Q_CE_1 <= L_CE_16 when L_CNT_16 = "1111" else '0'; 82 83 end behavioral; 84 <pre class="filename"> src/baudgen.vhd </pre></pre> <P> <P><hr><BR> <table class="ttop"><th class="tpre"><a href="11_Listing_of_avr_fpga.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="13_Listing_of_common.vhd.html">Next Lesson</a></th></table> </BODY> </HTML>