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[/] [datetime/] [trunk/] [rtl/] [verilog/] [sync2s.v] - Rev 2
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// two stage synchronizer module sync2s(rst, clk, i, o); input rst; input clk; input i; output o; reg [1:0] s; always @(posedge clk) if (rst) s <= 0; else s <= {s[0],i}; assign o = s[1]; endmodule