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https://opencores.org/ocsvn/desxcore/desxcore/trunk
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[/] [desxcore/] [trunk/] [rtl/] [s_box_dram_4.xco] - Rev 2
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################################################################ Xilinx Core Generator version 14.4# Date: Wed Feb 20 10:21:53 2013################################################################# This file contains the customisation parameters for a# Xilinx CORE Generator IP GUI. It is strongly recommended# that you do not manually alter this file as it may cause# unexpected and unsupported behavior.################################################################# Generated from component: xilinx.com:ip:dist_mem_gen:7.2################################################################# BEGIN Project OptionsSET addpads = falseSET asysymbol = trueSET busformat = BusFormatAngleBracketNotRippedSET createndf = falseSET designentry = VHDLSET device = xc7a200tSET devicefamily = artix7SET flowvendor = OtherSET formalverification = falseSET foundationsym = falseSET implementationfiletype = NgcSET package = fbg484SET removerpms = falseSET simulationfiles = BehavioralSET speedgrade = -3SET verilogsim = falseSET vhdlsim = true# END Project Options# BEGIN SelectSELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2# END Select# BEGIN ParametersCSET ce_overrides=ce_overrides_sync_controlsCSET coefficient_file=s_box_v_4.coeCSET common_output_ce=falseCSET common_output_clk=falseCSET component_name=s_box_dram_4CSET data_width=4CSET default_data=0CSET default_data_radix=16CSET depth=64CSET dual_port_address=non_registeredCSET dual_port_output_clock_enable=falseCSET input_clock_enable=falseCSET input_options=non_registeredCSET memory_type=romCSET output_options=non_registeredCSET pipeline_stages=0CSET qualify_we_with_i_ce=falseCSET reset_qdpo=falseCSET reset_qsdpo=falseCSET reset_qspo=falseCSET simple_dual_port_address=non_registeredCSET simple_dual_port_output_clock_enable=falseCSET single_port_output_clock_enable=falseCSET sync_reset_qdpo=falseCSET sync_reset_qsdpo=falseCSET sync_reset_qspo=false# END Parameters# BEGIN Extra informationMISC pkg_timestamp=2012-11-21T20:07:40Z# END Extra informationGENERATE# CRC: 58461591
