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[/] [dma_ahb/] [trunk/] [src/] [dma_ahb64/] [dma_ahb64_core0_ch_fifo_ctrl.v] - Rev 4
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///////////////////////////////////////////////////////////////////// //// //// //// Author: Eyal Hochberg //// //// eyal@provartec.com //// //// //// //// Downloaded from: http://www.opencores.org //// ///////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2010 Provartec LTD //// //// www.provartec.com //// //// info@provartec.com //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer.//// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation.//// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more//// //// details. http://www.gnu.org/licenses/lgpl.html //// //// //// ///////////////////////////////////////////////////////////////////// //--------------------------------------------------------- //-- File generated by RobustVerilog parser //-- Version: 1.0 //-- Invoked Fri Mar 25 23:33:02 2011 //-- //-- Source file: dma_ch_fifo_ctrl.v //--------------------------------------------------------- module dma_ahb64_core0_ch_fifo_ctrl (clk,reset,end_swap,joint_in_prog,wr_outstanding,ch_update,fifo_wr,fifo_wdata,fifo_wsize,wr_align,rd_incr,fifo_rd,fifo_rsize,rd_align,wr_incr,wr_single,wr_burst_size,rd_clr_line,wr_clr_line,wr_next_size,fifo_rd_valid,fifo_rdata,fifo_wr_ready,fifo_overflow,fifo_underflow); input clk; input reset; input [1:0] end_swap; input joint_in_prog; input wr_outstanding; input ch_update; input fifo_wr; input [64-1:0] fifo_wdata; input [4-1:0] fifo_wsize; input [3-1:0] wr_align; input rd_incr; input fifo_rd; input [4-1:0] fifo_rsize; input [3-1:0] rd_align; input wr_incr; input wr_single; input [8-1:0] wr_burst_size; input rd_clr_line; input wr_clr_line; input [4-1:0] wr_next_size; output fifo_rd_valid; output [64-1:0] fifo_rdata; output fifo_wr_ready; output fifo_overflow; output fifo_underflow; //outputs of wr slicer wire slice_wr; wire slice_wr_fifo; wire [5-1:0] slice_wr_ptr; wire [8-1:0] slice_bsel; wire [64-1:0] slice_wdata; wire [4-1:0] slice_wsize; //outputs of rd slicer wire slice_rd; wire [64-1:0] slice_rdata; wire [4-1:0] slice_rsize; wire [5-1:0] slice_rd_ptr; wire slice_rd_valid; //outputs of fifo ptr wire [5-1:0] rd_ptr; wire [5-1:0] wr_ptr; wire [4-1:0] rd_line_remain; wire joint_delay; wire fifo_wr_ready; wire fifo_overflow; wire fifo_underflow; //outputs of fifo wire [64-1:0] DOUT; wire fifo_wr_d; reg [64-1:0] fifo_wdata_d; wire fifo_wr_valid; wire [64-1:0] fifo_wdata_valid; prgen_delay #(1) delay_fifo_wr (.clk(clk), .reset(reset), .din(fifo_wr), .dout(fifo_wr_d)); always @(posedge clk or posedge reset) if (reset) fifo_wdata_d <= #1 {64{1'b0}}; else if (fifo_wr) fifo_wdata_d <= #1 fifo_wdata; assign fifo_wr_valid = joint_delay ? fifo_wr_d : fifo_wr; assign fifo_wdata_valid = joint_delay ? fifo_wdata_d : fifo_wdata; assign fifo_rdata = slice_rdata & {64{slice_rd_valid}}; assign fifo_rd_valid = slice_rd_valid; dma_ahb64_core0_ch_wr_slicer dma_ahb64_ch_wr_slicer ( .clk(clk), .reset(reset), .ch_update(ch_update), .rd_clr_line(rd_clr_line), .fifo_wr(fifo_wr_valid), .fifo_wdata(fifo_wdata_valid), .fifo_wsize(fifo_wsize), .wr_align(wr_align), .wr_ptr(wr_ptr), .rd_incr(rd_incr), .end_swap(end_swap), .slice_wr(slice_wr), .slice_wr_fifo(slice_wr_fifo), .slice_wr_ptr(slice_wr_ptr), .slice_bsel(slice_bsel), .slice_wdata(slice_wdata), .slice_wsize(slice_wsize) ); dma_ahb64_core0_ch_rd_slicer dma_ahb64_ch_rd_slicer ( .clk(clk), .reset(reset), .fifo_rd(fifo_rd), .fifo_rdata(DOUT), .fifo_rsize(fifo_rsize), .rd_align(rd_align), .rd_ptr(rd_ptr), .rd_line_remain(rd_line_remain), .wr_incr(wr_incr), .wr_single(wr_single), .slice_rd(slice_rd), .slice_rdata(slice_rdata), .slice_rd_valid(slice_rd_valid), .slice_rsize(slice_rsize), .slice_rd_ptr(slice_rd_ptr) ); dma_ahb64_core0_ch_fifo_ptr dma_ahb64_ch_fifo_ptr ( .clk(clk), .reset(reset), .joint_in_prog(joint_in_prog), .wr_outstanding(wr_outstanding), .ch_update(ch_update), .fifo_rd(fifo_rd), .fifo_rsize(fifo_rsize), .slice_wr(slice_wr), .slice_wr_fifo(slice_wr_fifo), .slice_wsize(slice_wsize), .slice_rd(slice_rd), .slice_rsize(slice_rsize), .rd_clr_line(rd_clr_line), .wr_clr_line(wr_clr_line), .rd_ptr(rd_ptr), .wr_ptr(wr_ptr), .rd_line_remain(rd_line_remain), .joint_delay(joint_delay), .wr_next_size(wr_next_size), .wr_burst_size(wr_burst_size), .fifo_wr_ready(fifo_wr_ready), .fifo_overflow(fifo_overflow), .fifo_underflow(fifo_underflow) ); dma_ahb64_core0_ch_fifo dma_ahb64_ch_fifo ( .CLK(clk), .WR(slice_wr_fifo), .RD(slice_rd), .WR_ADDR(slice_wr_ptr[5-1:3] ), .RD_ADDR(slice_rd_ptr[5-1:3]), .DIN(slice_wdata), .BSEL(slice_bsel), .DOUT(DOUT) ); endmodule