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//---------------------------------------------------------
//-- File generated by RobustVerilog parser
//-- Version: 1.0
//-- Invoked Fri Mar 25 23:32:59 2011
//--
//-- Source file: prgen_scatter.v
//---------------------------------------------------------
 
 
 
module prgen_scatter8_1(ch_x,x);
 
   parameter                  CH_NUM     = 0;
 
 
   input [8*1-1:0]    ch_x;
   output [8-1:0]         x;
 
 
   assign               x = {
                  ch_x[CH_NUM+7],
                  ch_x[CH_NUM+6],
                  ch_x[CH_NUM+5],
                  ch_x[CH_NUM+4],
                  ch_x[CH_NUM+3],
                  ch_x[CH_NUM+2],
                  ch_x[CH_NUM+1],
                  ch_x[CH_NUM+0]};
 
 
endmodule