Subversion Repositories graphicsaccelerator

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="/home/omar/LineFPGA/Bresenhammer_Sim_isim_beh.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="bresenhammer_sim" />
            <top_module name="numeric_std" />
            <top_module name="std_logic_1164" />
            <top_module name="std_logic_arith" />
            <top_module name="std_logic_unsigned" />
         </top_modules>
      </db_ref>
   </db_ref_list>
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      <obj_property name="ElementShortName">x1[9:0]</obj_property>
      <obj_property name="ObjectShortName">x1[9:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/bresenhammer_sim/y1" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">y1[8:0]</obj_property>
      <obj_property name="ObjectShortName">y1[8:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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      <obj_property name="ObjectShortName">x2[9:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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      <obj_property name="ObjectShortName">y2[8:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
   </wvobject>
   <wvobject fp_name="/bresenhammer_sim/clk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clk</obj_property>
      <obj_property name="ObjectShortName">clk</obj_property>
   </wvobject>
   <wvobject fp_name="/bresenhammer_sim/startdraw" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">startdraw</obj_property>
      <obj_property name="ObjectShortName">startdraw</obj_property>
   </wvobject>
   <wvobject fp_name="/bresenhammer_sim/reset" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">reset</obj_property>
      <obj_property name="ObjectShortName">reset</obj_property>
   </wvobject>
   <wvobject fp_name="/bresenhammer_sim/writeenable" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">writeenable</obj_property>
      <obj_property name="ObjectShortName">writeenable</obj_property>
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      <obj_property name="ElementShortName">x[9:0]</obj_property>
      <obj_property name="ObjectShortName">x[9:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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      <obj_property name="ObjectShortName">y[8:0]</obj_property>
      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
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      <obj_property name="ObjectShortName">ss[3:0]</obj_property>
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   <wvobject fp_name="/bresenhammer_sim/clk_period" type="other" db_ref_id="1">
      <obj_property name="ElementShortName">clk_period</obj_property>
      <obj_property name="ObjectShortName">clk_period</obj_property>
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