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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: nnARM</font></b><p><table  align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top"><tbody><tr bgcolor=#bbccff>    <td align=center valign=center>               
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<a href="./Introduction.shtml">Introduction</a>               |
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<a href="">Contact me</a>    </td></tr></tbody></table><p><center><font  color="#bf0000" size=+3><b>Introduction</b></font></center></p><font  color="000088"size=+1><b>1.Purpose of this project<br></b></font><font ><b><br>This project has two primary purposes:<br><br>FIRST: To develop a synthesizable embedded processor soft core.<br><br>SECOND: To give the project members experience in organizing a free hardware development team over the internet.  The GNU and Linux successes have proven that this development mode is successful for software, we want to prove it is also suitable for hardware development.<br><br></b></font><font  color="000088"size=+1><b>2.What help do we want?<br></b></font><font ><b><br>Currently, this is a very small team.  There is only one main developer, and one documentation person.  We can not imagine that such a small team can manage to create this entire system without additional design and testing help.  So any kind of help is welcomed.  If you are interest in this, please contact <a href=""></a><br><br>
First, this team is particularly weak in the design of cache and memory controllers, so we are eager for help in this field.<br><br>
Second,Help to test the core, both in the simulator or on an actual FPGA board.<br><br>
Third, help to port uclinux or  ECOS to nnARM<br><br></b></font>
<font  color="000088"size=+1><b>3.What it can do and can not do now<br></b></font>
<font ><b><br>Currently, this core can fully support ARMv4T ISA<br><br>
it does not support MMU and cache, so it can not run a OS that require Virtual memory <br><br></b></font><font  color="000088"size=+1><b>4.Books used as reference works:<br></b></font><font ><b><br>1.Books on architecture<br><br>Computer Architecture : A Quantitative Approach by John Hennessy, David Patterson(January 1996).<br><br>2.Books on RTL design and synthesis<br><br>HDL chip design by Douglas J Smith <br><br><br><br><font  color="000088"size=+1><b>5.Tools in use on the project:<br></b></font><font ><b><br>1. simulation tools<br><br>
VCS verilog simulator from workview office<br><br>Verilog-XL simulator from cadence<br><br>ModelSim Xilinx Edition<br><br>
2.RTL synthesis tools<br><br>Quartus II from Altera <br><br>Aurora from workview office<br><br>Design Compiler from synopsys<br><br>
3.ARM development tools<br><br>ARM SDT 2.5 from ARM<br><br>GCC for ARM.<br><br></b></font><!--# include virtual="/ssi/ssi_end.shtml" -->

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