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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: nnARM</font></b><p><table  align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top"><tbody><tr bgcolor=#bbccff>    <td align=center valign=center>               
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<a href="">Contact me</a>    </td></tr></tbody></table><p><font size=+1><b>Description</b></font><P>nnARM is a synthesizeable soft core that is compatible with ARM7. It is designed as a high performance core with compact size and low power consumption.<br><br>This core is very similar to ARM7 from a programmer's view, but its internal structure do not have any connection with ARM7. I redesign a brand new architecture for it.For detail of its architecture, please refer to  documentation section of this site.<p>All source code of current release will be available on this site for free,At the same time, I also include some asembly source code come from ARM SDT 2.5 as testbench for it. For detail of testbench, please refer to testbench section of this site.<p>Designer team of nnARM welcome any kinds of help from anybody, if you are interest in this project, please contact us.For detail of what help do we need, please refer to introduction section of this site.<br><br><BR><p>Current Status:<ul><li>This core now support most instructions of ARM7 </li><li>The pipeline interlock and result forwarding feature run correctly in all testbench </li><li>More detail about What it can do and what it can not do please refer to introduction section of this site </li></ul><p>Next Step:<ul><li>Make its memory and cache controller synthesizeable </li><li>Support more complex instruction such as data swap and block data transfer</li><li>Support more internal device such as Timer and DMA</li></ul><p>Maintainer(s):<ul><a href="">ShengYu Shen</a></ul><p>Mailing-list:<ul><a></A></ul><!--# include virtual="/ssi/ssi_end.shtml" -->

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