Subversion Repositories nnARM

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<b><font size=+2 face="Helvetica, Arial"color=#bf0000>Project Name: nnARM</font></b><p><table  align=center border=1 cellPadding=2 cellSpacing=0 width="100%" valign="top"><tbody><tr bgcolor=#bbccff>    <td align=center valign=center>               
<a href="./News.shtml">News</a>               |
<a href="./People.shtml">People</a>               |
<a href="./PR.shtml">Press & Release</a>               |
<a href="./Introduction.shtml">Introduction</a>               |
<a href="./Documentation.shtml">Documentation</a>               |
<a href="./Download.shtml">Download</a>               |
<a href="./Testbench/Testbench.shtml">Testbench</a>               |
<a href="./GT.shtml">GNU Tools</a>               |
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<a href="">Contact me</a>    </td></tr></tbody></table><p><font size=+1><b>Description</b></font><P>nnARM is a synthesizeable soft core that is compatible with ARM7. It is designed as a high performance core with compact size and low power consumption.<br><br>This core is very similar to ARM7 from a programmer's view, but its internal structure does not have any connection with that of ARM7.  It has been designed using a brand new architecture for it.  For details concerning this architecture, please refer to the documentation section of this site.<p>All source code of the current release is available on this site for free.  Also, there is some assembly source code (compiled on ARM SDT 2.5) used as part of a testbench for nnARM. For more details regarding this testbench, please refer to the testbench section of this site.<p>The design team of nnARM welcomes any kind of help from anybody, if you are interested in this project, please contact us.  For details of what help we need, please refer to introduction section of this site.<br><br><BR><p>Current Status:<ul><li>This core now supports most of the instructions of ARM7 </li><li>The pipeline interlock and result forwarding features run correctly in all testbenches.</li><li>For more detail about what it can do and what it can not do please refer to the introduction section of this site </li></ul><p>Next Step:<ul><li>Make its memory and cache controller synthesizeable.</li><li>Support more complex instructions such as data swap and block data transfer.</li><li>Support more internal devices such as Timer and DMA.</li></ul><p>Maintainer(s):<ul><a href="">ShengYu Shen</a></ul><p>Mailing-list:<ul><a></A></ul><!--# include virtual="/ssi/ssi_end.shtml" -->

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