URL
https://opencores.org/ocsvn/orsoc_graphics_accelerator/orsoc_graphics_accelerator/trunk
Subversion Repositories orsoc_graphics_accelerator
[/] [orsoc_graphics_accelerator/] [trunk/] [bench/] [verilog/] [gfx/] [Makefile] - Rev 6
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WFLAGS = -Wall -Wno-timescale -I../../../rtl/verilog/gfx/all: gfxupdate:iverilog $(WFLAGS) gfx_bench.v./a.outiverilog $(WFLAGS) raster_bench.v./a.outiverilog $(WFLAGS) renderer_bench.v./a.outiverilog $(WFLAGS) clip_bench.v./a.outiverilog $(WFLAGS) fragment_bench.v./a.outiverilog $(WFLAGS) blender_bench.v./a.outiverilog $(WFLAGS) wbm_w_bench.v./a.outiverilog $(WFLAGS) wbm_r_bench.v./a.outiverilog $(WFLAGS) color_bench.v./a.outiverilog $(WFLAGS) wbm_arbiter_bench.v./a.outiverilog $(WFLAGS) line_bench.v./a.outiverilog $(WFLAGS) transform_bench.v./a.outiverilog $(WFLAGS) triangle_bench.v./a.outiverilog $(WFLAGS) div_bench.v./a.outiverilog $(WFLAGS) interp_bench.v./a.outiverilog $(WFLAGS) fifo_bench.v./a.outiverilog $(WFLAGS) cuvz_bench.v./a.outgfx:iverilog $(WFLAGS) gfx_bench.v./a.outgtkwave gfx.vcd gtkwave_gfx.savraster:iverilog $(WFLAGS) raster_bench.v./a.outgtkwave raster.vcd gtkwave_raster.savrender:iverilog $(WFLAGS) renderer_bench.v./a.outgtkwave render.vcd gtkwave_render.savclip:iverilog $(WFLAGS) clip_bench.v./a.outgtkwave clip.vcd gtkwave_clip.savfragment:iverilog $(WFLAGS) fragment_bench.v./a.outgtkwave fragment.vcd gtkwave_fragment.savblender:iverilog $(WFLAGS) blender_bench.v./a.outgtkwave blender.vcd gtkwave_blender.savwbm_w:iverilog $(WFLAGS) wbm_w_bench.v./a.outgtkwave wbm_w.vcd gtkwave_wbm_w.savwbm_r:iverilog $(WFLAGS) wbm_r_bench.v./a.outgtkwave wbm_r.vcd gtkwave_wbm_r.savcolor:iverilog $(WFLAGS) color_bench.v./a.outgtkwave color.vcd gtkwave_color.savarbiter:iverilog $(WFLAGS) wbm_arbiter_bench.v./a.outgtkwave arbiter.vcdline:iverilog $(WFLAGS) line_bench.v./a.outgtkwave line.vcd line.savtransform:iverilog $(WFLAGS) transform_bench.v./a.outgtkwave transform.vcd transform.savtriangle:iverilog $(WFLAGS) triangle_bench.v./a.outgtkwave triangle.vcd triangle.savdiv:iverilog $(WFLAGS) div_bench.v./a.outgtkwave div.vcd div.savinterp:iverilog $(WFLAGS) interp_bench.v./a.outgtkwave interp.vcd interp.savcuvz:iverilog $(WFLAGS) cuvz_bench.v./a.outgtkwave cuvz.vcd cuvz.savfifo:iverilog $(WFLAGS) fifo_bench.v./a.outgtkwave fifo.vcd fifo.sav
