Subversion Repositories raggedstone

This logic is for the Enterpoint Spartan-3 based PCI fpga card.

The code needs to be built with the Xilinx tools. You can
download the Xilinx tools for free from xilinx.com. It also
generates a bit of the VHDL by perl, so you need that installed
also.

Steps to building & using this code:

1) Install Linux (it should include perl)
2) Download and install the Xilinx WebPack for Linux
        * It's about 1GB and Xilinx provides it for free
        * The Xilinx tools include a settings.sh file
          that you need to run to add the tools to your path
3) Run make to synthisize the image
4) program your card over jtag with XC3prog
        xc3sprog pci_7seg.bit


This port of the OpenCores PCI core was originally done by Manuel Bessler.
http://projects.varxec.net/raggedstone1

If you get this core installed correctly on the Raggedstone1 card, you
can dump out the PCI config space and it should look something like this:

root@sid:~# hexdump /proc/bus/pci/05/02.0
0000000 10ee 0100 0102 0200 0037 0280 0000 0000
0000010 0000 f800 0000 0000 0000 0000 0000 0000
0000020 0000 0000 0000 0000 0000 0000 0480 1558
0000030 0000 0000 0000 0000 0000 0000 0104 0000
0000040 0000 0000 5671 1234 5672 1234 5673 1234
0000050 5674 1234 5675 1234 5676 1234 5677 1234
0000060 5678 1234 5679 1234 5680 1234 5681 1234
0000070 5682 1234 5683 1234 5684 1234 5685 1234
0000080 5686 1234 5687 1234 5688 1234 5689 1234
0000090 5690 1234 5691 1234 5692 1234 5693 1234
00000a0 5694 1234 5695 1234 5696 1234 5697 1234
00000b0 5698 1234 5699 1234 5700 1234 5701 1234
00000c0 5702 1234 5703 1234 5704 1234 5705 1234
00000d0 5706 1234 5707 1234 5708 1234 5709 1234
00000e0 5710 1234 5711 1234 5712 1234 0000 0000
00000f0 0000 0000 0000 0000 0000 0000 0000 0000
0000100

-- Jeff Carr <basilarchia@gmail.com>