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RAM Summary report for cycloneIII_3c25_niosII_videoWed Aug 15 10:41:19 2012Quartus II Version 11.0 Build 157 04/27/2011 SJ Web Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter RAM Summary----------------; Legal Notice ;----------------Copyright (C) 1991-2011 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------+----------------------------------------------------------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------+----------------------------------------------------------------+; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu:the_cpu|cpu_ic_data_module:cpu_ic_data|altsyncram:the_altsyncram|altsyncram_tcd1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 1 ; None ; M9K_X22_Y27_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu:the_cpu|cpu_ic_tag_module:cpu_ic_tag|altsyncram:the_altsyncram|altsyncram_v0g1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 25 ; 32 ; 25 ; yes ; no ; yes ; no ; 800 ; 32 ; 25 ; 32 ; 25 ; 800 ; 1 ; cpu_ic_tag_ram.mif ; M9K_X22_Y31_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_ocimem:the_cpu_nios2_ocimem|cpu_ociram_lpm_dram_bdp_component_module:cpu_ociram_lpm_dram_bdp_component|altsyncram:the_altsyncram|altsyncram_6472:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Single Clock ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 2 ; cpu_ociram_default_contents.mif ; M9K_X22_Y28_N0, M9K_X22_Y29_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu:the_cpu|cpu_register_bank_a_module:cpu_register_bank_a|altsyncram:the_altsyncram|altsyncram_cqf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; cpu_rf_ram_a.mif ; M9K_X22_Y32_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu:the_cpu|cpu_register_bank_b_module:cpu_register_bank_b|altsyncram:the_altsyncram|altsyncram_dqf1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 32 ; 32 ; 32 ; yes ; no ; yes ; no ; 1024 ; 32 ; 32 ; 32 ; 32 ; 1024 ; 1 ; cpu_rf_ram_b.mif ; M9K_X22_Y30_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu_ddr_clock_bridge:the_cpu_ddr_clock_bridge|cpu_ddr_clock_bridge_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_1tf1:auto_generated|altsyncram_ni31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 8 ; 86 ; 8 ; 86 ; yes ; no ; yes ; yes ; 688 ; 8 ; 62 ; 8 ; 62 ; 496 ; 2 ; None ; M9K_X22_Y25_N0, M9K_X22_Y24_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cpu_ddr_clock_bridge:the_cpu_ddr_clock_bridge|cpu_ddr_clock_bridge_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|altsyncram_di31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 33 ; 64 ; 33 ; yes ; no ; yes ; yes ; 2112 ; 64 ; 32 ; 64 ; 32 ; 2048 ; 1 ; None ; M9K_X22_Y26_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|cycloneIII_3c25_niosII_video_sopc_burst_1:the_cycloneIII_3c25_niosII_video_sopc_burst_1|cycloneIII_3c25_niosII_video_sopc_burst_1_fifo_module:the_cycloneIII_3c25_niosII_video_sopc_burst_1_fifo_module|cycloneIII_3c25_niosII_video_sopc_burst_1_fifo_module_fifo_ram_module:cycloneIII_3c25_niosII_video_sopc_burst_1_fifo_module_fifo_ram|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|altsyncram:ram_block|altsyncram_kbq1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 64 ; 16 ; 64 ; yes ; no ; yes ; no ; 1024 ; 16 ; 64 ; 16 ; 64 ; 1024 ; 2 ; None ; M9K_X22_Y14_N0, M9K_X22_Y13_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|ddr_sdram:the_ddr_sdram|ddr_sdram_controller_phy:ddr_sdram_controller_phy_inst|ddr_sdram_auk_ddr_hp_controller_wrapper:ddr_sdram_auk_ddr_hp_controller_wrapper_inst|auk_ddr_hp_controller:auk_ddr_hp_controller_inst|auk_ddr_hp_avalon_if:\g_local_avalon_if:av_if|scfifo:wfifo|scfifo_jve1:auto_generated|a_dpfifo_kg71:dpfifo|altsyncram_1ea1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 72 ; 32 ; 72 ; yes ; no ; yes ; no ; 2304 ; 32 ; 72 ; 32 ; 72 ; 2304 ; 2 ; None ; M9K_X22_Y15_N0, M9K_X22_Y16_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|ddr_sdram:the_ddr_sdram|ddr_sdram_controller_phy:ddr_sdram_controller_phy_inst|ddr_sdram_phy:ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy:ddr_sdram_phy_alt_mem_phy_inst|ddr_sdram_phy_alt_mem_phy_rdata_valid:rdv_pipe|altsyncram:altsyncram_component|altsyncram_4ni1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 2 ; 32 ; 2 ; yes ; no ; yes ; yes ; 64 ; 32 ; 2 ; 32 ; 2 ; 64 ; 1 ; None ; M9K_X33_Y22_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|ddr_sdram:the_ddr_sdram|ddr_sdram_controller_phy:ddr_sdram_controller_phy_inst|ddr_sdram_phy:ddr_sdram_phy_inst|ddr_sdram_phy_alt_mem_phy:ddr_sdram_phy_alt_mem_phy_inst|ddr_sdram_phy_alt_mem_phy_read_dp:rdp|altsyncram:half_rate_ram_gen.altsyncram_component|altsyncram_7ch1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 16 ; 32 ; 8 ; 64 ; yes ; no ; yes ; yes ; 512 ; 16 ; 32 ; 8 ; 64 ; 512 ; 2 ; None ; M9K_X33_Y15_N0, M9K_X33_Y16_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|lcd_pixel_fifo:the_lcd_pixel_fifo|lcd_pixel_fifo_dcfifo_with_controls:the_dcfifo_with_controls|lcd_pixel_fifo_dual_clock_fifo:the_dcfifo|dcfifo:dual_clock_fifo|dcfifo_tpg1:auto_generated|altsyncram_1j31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 69 ; 128 ; 69 ; yes ; no ; yes ; yes ; 8832 ; 128 ; 53 ; 128 ; 53 ; 6784 ; 2 ; None ; M9K_X33_Y29_N0, M9K_X33_Y28_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|lcd_sgdma:the_lcd_sgdma|lcd_sgdma_command_fifo:the_lcd_sgdma_command_fifo|scfifo:lcd_sgdma_command_fifo_command_fifo|scfifo_2c31:auto_generated|a_dpfifo_9i31:dpfifo|altsyncram_qsd1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2 ; 104 ; 2 ; 104 ; yes ; no ; yes ; yes ; 208 ; 2 ; 41 ; 2 ; 41 ; 82 ; 2 ; None ; M9K_X22_Y20_N0, M9K_X22_Y21_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|lcd_sgdma:the_lcd_sgdma|lcd_sgdma_m_readfifo:the_lcd_sgdma_m_readfifo|lcd_sgdma_m_readfifo_m_readfifo:the_lcd_sgdma_m_readfifo_m_readfifo|scfifo:lcd_sgdma_m_readfifo_m_readfifo_m_readfifo|scfifo_ru31:auto_generated|a_dpfifo_2541:dpfifo|altsyncram_std1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 32 ; 69 ; 32 ; 69 ; yes ; no ; yes ; yes ; 2208 ; 32 ; 53 ; 32 ; 53 ; 1696 ; 2 ; None ; M9K_X33_Y25_N0, M9K_X33_Y24_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|lcd_sgdma:the_lcd_sgdma|lcd_sgdma_status_token_fifo:the_lcd_sgdma_status_token_fifo|scfifo:lcd_sgdma_status_token_fifo_status_token_fifo|scfifo_ja31:auto_generated|a_dpfifo_qg31:dpfifo|altsyncram_spd1:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2 ; 24 ; 2 ; 24 ; yes ; no ; yes ; yes ; 48 ; 2 ; 24 ; 2 ; 24 ; 48 ; 1 ; None ; M9K_X22_Y18_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_0:the_raytrac_0|raytrac:raytrac_0|ap_n_dpc:arithmetic_pipeline_and_datapath_controller|arithblock:ap|invr32:inversion_block|altsyncram:altsyncram_component|altsyncram_b8a1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 1024 ; 18 ; -- ; -- ; yes ; no ; -- ; -- ; 18432 ; 1024 ; 17 ; -- ; -- ; 17408 ; 2 ; ./meminvr.mif ; M9K_X33_Y5_N0, M9K_X33_Y6_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_0:the_raytrac_0|raytrac:raytrac_0|ap_n_dpc:arithmetic_pipeline_and_datapath_controller|arithblock:ap|sqrt32:square_root|altsyncram:altsyncram_component|altsyncram_m8a1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; Single Clock ; 1024 ; 18 ; -- ; -- ; yes ; no ; -- ; -- ; 18432 ; 1024 ; 17 ; -- ; -- ; 17408 ; 2 ; ./memsqrt.mif ; M9K_X33_Y4_N0, M9K_X33_Y3_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_0:the_raytrac_0|raytrac:raytrac_0|ap_n_dpc:arithmetic_pipeline_and_datapath_controller|scfifo:qxqyqz|scfifo_gi61:auto_generated|a_dpfifo_34v:dpfifo|altsyncram_8d81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 96 ; 32 ; 96 ; yes ; no ; yes ; no ; 3072 ; 32 ; 96 ; 32 ; 96 ; 3072 ; 3 ; None ; M9K_X33_Y7_N0, M9K_X33_Y8_N0, M9K_X33_Y9_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_0:the_raytrac_0|raytrac:raytrac_0|scfifo:output_buffer|scfifo_4u91:auto_generated|a_dpfifo_qqv:dpfifo|altsyncram_ag81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 32 ; 256 ; 32 ; yes ; no ; yes ; no ; 8192 ; 256 ; 32 ; 256 ; 32 ; 8192 ; 1 ; None ; M9K_X33_Y14_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_0:the_raytrac_0|raytrac:raytrac_0|scfifo:res|scfifo_lo61:auto_generated|a_dpfifo_8av:dpfifo|altsyncram_mj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 128 ; 256 ; 128 ; yes ; no ; yes ; no ; 32768 ; 256 ; 128 ; 256 ; 128 ; 32768 ; 4 ; None ; M9K_X33_Y11_N0, M9K_X33_Y12_N0, M9K_X33_Y10_N0, M9K_X33_Y13_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_ddr_clock_crossing_bridge:the_raytrac_ddr_clock_crossing_bridge|raytrac_ddr_clock_crossing_bridge_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_h7g1:auto_generated|altsyncram_3l31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 33 ; 1024 ; 33 ; yes ; no ; yes ; yes ; 33792 ; 1024 ; 32 ; 1024 ; 32 ; 32768 ; 4 ; None ; M9K_X22_Y10_N0, M9K_X22_Y11_N0, M9K_X22_Y12_N0, M9K_X22_Y9_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_ssram_clock_crossing_bridge:the_raytrac_ssram_clock_crossing_bridge|raytrac_ssram_clock_crossing_bridge_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_7tf1:auto_generated|altsyncram_ti31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 8 ; 89 ; 8 ; 89 ; yes ; no ; yes ; yes ; 712 ; 8 ; 66 ; 8 ; 66 ; 528 ; 2 ; None ; M9K_X33_Y19_N0, M9K_X33_Y21_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|raytrac_ssram_clock_crossing_bridge:the_raytrac_ssram_clock_crossing_bridge|raytrac_ssram_clock_crossing_bridge_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_i3g1:auto_generated|altsyncram_ji31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 33 ; 512 ; 33 ; yes ; no ; yes ; yes ; 16896 ; 512 ; 32 ; 512 ; 32 ; 16384 ; 2 ; None ; M9K_X33_Y26_N0, M9K_X33_Y27_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|slow_peripheral_bridge:the_slow_peripheral_bridge|slow_peripheral_bridge_downstream_fifo:the_downstream_fifo|dcfifo:downstream_fifo|dcfifo_cuf1:auto_generated|altsyncram_ki31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 16 ; 56 ; 16 ; 56 ; yes ; no ; yes ; yes ; 896 ; 16 ; 49 ; 16 ; 49 ; 784 ; 2 ; None ; M9K_X22_Y17_N0, M9K_X22_Y19_N0 ;; cycloneIII_3c25_niosII_video_sopc:cycloneIII_3c25_niosII_video_sopc_instance|slow_peripheral_bridge:the_slow_peripheral_bridge|slow_peripheral_bridge_upstream_fifo:the_upstream_fifo|dcfifo:upstream_fifo|dcfifo_u1g1:auto_generated|altsyncram_di31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 64 ; 33 ; 64 ; 33 ; yes ; no ; yes ; yes ; 2112 ; 64 ; 32 ; 64 ; 32 ; 2048 ; 1 ; None ; M9K_X22_Y8_N0 ;+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+---------------------------------+----------------------------------------------------------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.