Subversion Repositories soc_maker

SOCM_CORE
name: adv_debug_sys
description: Advanced Debug System
version: ads_3
license: LGPL
licensefile: 
author: 
authormail: 
vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
toplevel: adbg_top

interfaces:



  :jtag: SOCM_IFC
    name: jtag_tap
    dir: 1
    version: "1"
    ports:
      :tck_i: SOCM_PORT
        len: 1
        defn: tck
      :tdi_i: SOCM_PORT
        len: 1
        defn: tdi
      :tdo_o: SOCM_PORT
        len: 1
        defn: tdo
      :rst_i: SOCM_PORT
        len: 1
        defn: rst

      :shift_dr_i: SOCM_PORT
        len: 1
        defn: shift
      :pause_dr_i: SOCM_PORT
        len: 1
        defn: pause
      :update_dr_i: SOCM_PORT
        len: 1
        defn: update
      :capture_dr_i: SOCM_PORT
        len: 1
        defn: capture
      :debug_select_i: SOCM_PORT
        len: 1
        defn: select




  :wb_ifc: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :wb_clk_i: SOCM_PORT
        len: 1
        defn: clk
      :wb_rst_i: SOCM_PORT
        len: 1
        defn: rst
      :wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :wb_dat_i: SOCM_PORT
        defn: dat_o
        len:  32
      :wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :wb_cab_o: SOCM_PORT
        defn: cab
        len:  1
      :wb_err_i: SOCM_PORT
        defn: err
        len:  1
      :wb_cti_o: SOCM_PORT
        defn: cti
        len:  3
      :wb_bte_o: SOCM_PORT
        defn: bte
        len:  2

  :cpu0_dbg_clk: SOCM_IFC
    name: clk
    dir: 1
    version: "1"
    ports:
      :cpu0_clk_i: SOCM_PORT
        len: 1
        defn: clk

  :cpu0_dbg_rst: SOCM_IFC
    name: rst
    dir: 0
    version: "1"
    ports:
      :cpu0_rst_o: SOCM_PORT
        len: 1
        defn: rst

  :cpu0_dbg: SOCM_IFC
    name: debug
    dir: 0
    version: "1"
    ports:
      :cpu0_addr_o: SOCM_PORT
        len: 32
        defn: dbg_adr   
      :cpu0_data_o: SOCM_PORT
        len: 32
        defn: dbg_dat_o
      :cpu0_data_i: SOCM_PORT
        len: 32
        defn: dbg_dat_i
      :cpu0_bp_i: SOCM_PORT
        len: 1
        defn: dbg_bpo   
      :cpu0_stall_o: SOCM_PORT
        defn: dbg_stall 
        len: 1
      :cpu0_stb_o: SOCM_PORT
        len: 1
        defn: dbg_stb   
      :cpu0_we_o: SOCM_PORT
        len: 1
        defn: dbg_we    
      :cpu0_ack_i: SOCM_PORT
        len: 1
        defn: dbg_ack   

#     :dbg_ewt_i: SOCM_PORT
#       len: 1
#       defn: dbg_ewt   
#     :dbg_lss_o: SOCM_PORT
#       len: 4
#       defn: dbg_lss   
#     :dbg_is_o: SOCM_PORT
#       len: 2
#       defn: dbg_iso   
#     :dbg_wp_o: SOCM_PORT
#       len: 11
#       defn: dbg_wpo    


hdlfiles:
  :adbg_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_top.v            

  :adbg_crc32: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_crc32.v
  :adbg_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_defines.v
  :adbg_jsp_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_jsp_biu.v
  :adbg_jsp_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_jsp_module.v
  :adbg_or1k_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_biu.v
  :adbg_or1k_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_defines.v
  :adbg_or1k_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_module.v
  :adbg_or1k_status_reg: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_or1k_status_reg.v
  :adbg_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_top.v
  :adbg_wb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_biu.v
  :adbg_wb_defines: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_defines.v
  :adbg_wb_module: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/adbg_wb_module.v
  :bytefifo: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/bytefifo.v
  :syncflow: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/syncflop.v
  :syncreg: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/syncreg.v