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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [or1200_rel2/] [02_or1200_files.yaml] - Rev 8

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hdlfiles:
  :alu: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/or1200_alu.v            

  :tlb: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: rtl/verilog/or1200_dmmu_tlb.v       

  :ram: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_ram.v    

  :operandmuxes: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_operandmuxes.v      

  :spram_1024: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x32.v     

  :spram_64_22: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x22.v

  :amultp2: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_amultp2_32x32.v  

  :dmmu_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dmmu_top.v       

  :ic_tag: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_tag.v    

  :pic: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_pic.v               

  :spram_1024_8: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x8.v      

  :spram_64_24: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x24.v

  :cfgr: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_cfgr.v           

  :dpram_256_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dpram_256x32.v   

  :ic_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_top.v    

  :pm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_pm.v                

  :spram_128_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_128x32.v      

  :sprs: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sprs.v

  :cpu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_cpu.v            

  :dpram_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dpram_32x32.v    

  :if: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_if.v        

  :qmem_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_qmem_top.v          

  :spram_2048_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x32_bw.v  

  :top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_top.v

  :or1200_ctrl: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ctrl.v           

  :du: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_du.v             

  :immu_tlb: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_immu_tlb.v  

  :reg2mem: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_reg2mem.v           

  :spram_2048_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x32.v     

  :tpram_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_tpram_32x32.v

  :dc_fsm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_fsm.v         

  :except: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_except.v         

  :immu_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_immu_top.v  

  :rfram_generic: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_rfram_generic.v     

  :spram_2048_8: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_2048x8.v      

  :tt: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_tt.v

  :dc_ram: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_ram.v         

  :freeze: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_freeze.v         

  :iwb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_iwb_biu.v   

  :rf: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_rf.v                

  :spram_256_21: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_256x21.v      

  :wb_biu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_wb_biu.v

  :dc_tag: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_tag.v         

  :genpc: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_genpc.v          

  :lsu: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_lsu.v       

  :fifo: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sb_fifo.v           

  :spram_32_24: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_32x24.v       

  :wbmux: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_wbmux.v

  :dc_top: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_dc_top.v         

  :gmultp2_32_32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_gmultp2_32x32.v  

  :mem2reg: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_mem2reg.v   

  :sb: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_sb.v                

  :spram_512_20: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_512x20.v      

  :xcv_ram32_8d: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_xcv_ram32x8d.v

# Please note: the defines is automatically created
# see or1200_defines.v.in

# :defines: SOCM_HDL_FILE
#   use_syn: true
#   use_sys_sim: true
#   use_mod_sim: true
#   type: vhdl
#   path: rtl/verilog/or1200_defines.v        

  :ic_fsm: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_ic_fsm.v         

  :mult_mac: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_mult_mac.v  

  :spram_2014x32: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_1024x32_bw.v  

  :spram_64_14: SOCM_HDL_FILE
    use_syn: true
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/or1200_spram_64x14.v       

  :timescale: SOCM_HDL_FILE
    use_syn: false
    use_sys_sim: true
    use_mod_sim: true
    type: vhdl
    path: rtl/verilog/timescale.v

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