Subversion Repositories soc_maker

SOCM_CORE
name: Wishbone RAM
description: Onchip-RAM
id: ram_wb,b3
license: LGPL
licensefile: 
author: 
authormail: 
vccmd: 
toplevel: ram_wb_b3

interfaces:
  :wb_ifc: SOCM_IFC
    name: Wishbone IFC
    dir: 1
    id: wishbone_sl,b3
    ports:
      :wb_adr_i: SOCM_PORT
        len: 32
        defn: adr
      :wb_bte_i: SOCM_PORT
        len: 2
        defn: bte
      :wb_cti_i: SOCM_PORT
        len: 3
        defn: cti
      :wb_cyc_i: SOCM_PORT
        len: 1
        defn: cyc
      :wb_dat_i: SOCM_PORT
        len: 32
        defn: dat_o
      :wb_sel_i: SOCM_PORT
        len: 4
        defn: sel
      :wb_stb_i: SOCM_PORT
        len: 1
        defn: stb
      :wb_we_i: SOCM_PORT
        len: 1
        defn: we
      :wb_ack_o: SOCM_PORT
        len: 1
        defn: ack
      :wb_err_o: SOCM_PORT
        len: 1
        defn: err
      :wb_rty_o: SOCM_PORT
        len: 1
        defn: rty
      :wb_dat_o: SOCM_PORT
        len: 32
        defn: dat_i
      :wb_clk_i: SOCM_PORT
        len: 1
        defn: clk
      :wb_rst_i: SOCM_PORT
        len: 1
        defn: rst

static_parameters:
  :ram_wb_b3: SOCM_SPARAM
    dir: .
    path: ./ram_wb_b3.v.in
    file_dst: ram_wb_b3.v
    parameters: 

      :MEM_SIZE: SOCM_SENTRY
         token: TOK_MEM_SIZE
         type:  integer
         visible: true
         editable: true
         default: 20

      :MEM_ADR_WIDTH: SOCM_SENTRY
         token: TOK_MEM_ADR_WIDTH
         type:  integer
         visible: true
         editable: true
         default: 15