Subversion Repositories soc_maker

SOCM_CORE
name: wb_connect
description: A block to connect RISC and peripheral controllers together
id: wb_connect,1
license: LGPL
licensefile: 
author: Damjan Lampret 
authormail: lampret@opencores.org
toplevel: minsoc_tc_top 
interfaces:


  :clk: SOCM_IFC
    name: clk
    dir: 1
    id: clk,1
    ports:
      :wb_clk_i: SOCM_PORT
        len: 1
        defn: clk
  
  :rst: SOCM_IFC
    name: rst
    dir: 1
    id: rst,1
    ports:
      :wb_rst_i: SOCM_PORT
        len: 1
        defn: rst



  :i0: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i0_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i0_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i0_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i0_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i0_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i0_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i0_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i0_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i0_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i0_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i1: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i1_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i1_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i1_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i1_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i1_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i1_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i1_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i1_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i1_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i1_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i2: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i2_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i2_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i2_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i2_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i2_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i2_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i2_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i2_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i2_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i2_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i3: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i3_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i3_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i3_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i3_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i3_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i3_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i3_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i3_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i3_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i3_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i4: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i4_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i4_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i4_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i4_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i4_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i4_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i4_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i4_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i4_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i4_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i5: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i5_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i5_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i5_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i5_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i5_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i5_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i5_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i5_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i5_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i5_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i6: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i6_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i6_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i6_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i6_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i6_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i6_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i6_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i6_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i6_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i6_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i7: SOCM_IFC
    name: wishbone_ma
    dir: 0
    id: wishbone_ma,b3
    ports:
      :i7_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :i7_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :i7_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i7_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i7_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i7_wb_sel_i: SOCM_PORT
        defn: sel
        len:  4
      :i7_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i7_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i7_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i7_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :t0: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t0_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t0_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t0_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t0_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t0_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t0_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t0_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t0_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t0_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t0_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t1: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t1_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t1_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t1_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t1_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t1_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t1_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t1_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t1_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t1_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t1_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t2: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t2_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t2_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t2_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t2_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t2_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t2_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t2_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t2_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t2_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t2_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t3: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t3_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t3_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t3_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t3_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t3_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t3_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t3_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t3_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t3_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t3_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t4: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t4_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t4_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t4_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t4_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t4_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t4_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t4_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t4_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t4_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t4_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t5: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t5_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t5_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t5_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t5_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t5_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t5_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t5_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t5_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t5_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t5_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t6: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t6_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t6_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t6_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t6_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t6_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t6_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t6_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t6_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t6_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t6_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t7: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t7_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t7_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t7_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t7_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t7_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t7_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t7_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t7_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t7_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t7_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t8: SOCM_IFC
    name: wishbone_sl
    dir: 0
    id: wishbone_sl,b3
    ports:
      :t8_wb_clk_o: SOCM_PORT
        defn: clk
        len:  1
      :t8_wb_rst_o: SOCM_PORT
        defn: rst
        len:  1
      :t8_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t8_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t8_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t8_wb_sel_o: SOCM_PORT
        defn: sel
        len:  4
      :t8_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t8_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :t8_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t8_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t8_wb_err_i: SOCM_PORT
        defn: err
        len:  1




hdlfiles:
  :minsoc_tc_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: minsoc_tc_top.v