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[/] [soc_maker/] [trunk/] [spec/] [test_soc_lib/] [cores/] [core_B_rel1/] [core_b.vhd] - Rev 10

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library ieee;
use ieee.std_logic_1164.ALL;
 
 
 
entity core_b is
port(
   mysig_con1a : out std_logic_vector( 7 downto 0 );
   mysig_con1b : out std_logic_vector( 31 downto 0 );
   mysig_con1c : in  std_logic
);
end entity core_b;
 
architecture IMPL of core_b is
 
 
begin
 
 
   mysig_con1a <= "11001010";
   mysig_con1b <= ( others => '1' );
 
end architecture IMPL;
 
 
 

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