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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [prev_cmp_spw_fifo_ulight.qmsg] - Rev 32
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1503605346490 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 24 17:09:06 2017 " "Processing started: Thu Aug 24 17:09:06 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346525 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346527 ""}{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../rtl/fpga_debug/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376205 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376207 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376207 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376208 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376208 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376209 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376211 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376211 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376215 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376217 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376222 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../rtl/fpga_debug/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376224 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376224 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../rtl/fpga_debug/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376226 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376231 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376233 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376235 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376235 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376269 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376270 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376270 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376271 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376274 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376274 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!:%2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376275 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376276 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376276 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376278 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376278 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376282 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376286 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376287 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376294 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376302 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376303 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376306 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376308 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376309 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376311 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376315 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376315 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376319 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376321 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376325 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 }} } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376328 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376332 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376332 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376335 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376338 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376342 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376345 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376352 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376352 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376356 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376358 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376360 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376362 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376364 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376366 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376368 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376371 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376377 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376379 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376454 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376457 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376461 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376463 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376465 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376467 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376470 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376474 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376476 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376478 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376481 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376483 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376493 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376495 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376508 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376510 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376511 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376513 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376515 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376517 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376517 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376519 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376521 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376523 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376525 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376525 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376527 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376527 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376530 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(96) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 96 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376532 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376533 ""}{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1503605376809 ""}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376811 "|SPW_ULIGHT_FIFO"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376816 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376829 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376834 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376838 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376843 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376847 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376853 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376880 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376896 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376914 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376927 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376937 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376944 ""}{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376950 ""}{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376960 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376962 ""}{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376971 ""}{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376978 ""}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376982 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376985 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377094 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377115 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377125 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377142 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377201 ""}{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377202 ""}{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_ac