Subversion Repositories spacewiresystemc

|SPW_ULIGHT_FIFO
FPGA_CLK1_50 => FPGA_CLK1_50.IN2
KEY[0] => ~NO_FANOUT~
KEY[1] => KEY[1].IN1
din_a => din_a.IN1
sin_a => sin_a.IN1
dout_a << dout_a.DB_MAX_OUTPUT_PORT_TYPE
sout_a << sout_a.DB_MAX_OUTPUT_PORT_TYPE
LED[0] << ulight_fifo:u0.led_pio_test_external_connection_export
LED[1] << ulight_fifo:u0.led_pio_test_external_connection_export
LED[2] << ulight_fifo:u0.led_pio_test_external_connection_export
LED[3] << ulight_fifo:u0.led_pio_test_external_connection_export
LED[4] << ulight_fifo:u0.led_pio_test_external_connection_export
LED[5] << debounce_db:db_system_spwulight_b.PB_down
LED[6] << <GND>
LED[7] << pll_tx_locked_export.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0
auto_start_external_connection_export <= ulight_fifo_auto_start:auto_start.out_port
clk_clk => clk_clk.IN27
clock_sel_external_connection_export[0] <= ulight_fifo_clock_sel:clock_sel.out_port
clock_sel_external_connection_export[1] <= ulight_fifo_clock_sel:clock_sel.out_port
clock_sel_external_connection_export[2] <= ulight_fifo_clock_sel:clock_sel.out_port
counter_rx_fifo_external_connection_export[0] => counter_rx_fifo_external_connection_export[0].IN1
counter_rx_fifo_external_connection_export[1] => counter_rx_fifo_external_connection_export[1].IN1
counter_rx_fifo_external_connection_export[2] => counter_rx_fifo_external_connection_export[2].IN1
counter_rx_fifo_external_connection_export[3] => counter_rx_fifo_external_connection_export[3].IN1
counter_rx_fifo_external_connection_export[4] => counter_rx_fifo_external_connection_export[4].IN1
counter_rx_fifo_external_connection_export[5] => counter_rx_fifo_external_connection_export[5].IN1
counter_tx_fifo_external_connection_export[0] => counter_tx_fifo_external_connection_export[0].IN1
counter_tx_fifo_external_connection_export[1] => counter_tx_fifo_external_connection_export[1].IN1
counter_tx_fifo_external_connection_export[2] => counter_tx_fifo_external_connection_export[2].IN1
counter_tx_fifo_external_connection_export[3] => counter_tx_fifo_external_connection_export[3].IN1
counter_tx_fifo_external_connection_export[4] => counter_tx_fifo_external_connection_export[4].IN1
counter_tx_fifo_external_connection_export[5] => counter_tx_fifo_external_connection_export[5].IN1
data_flag_rx_external_connection_export[0] => data_flag_rx_external_connection_export[0].IN1
data_flag_rx_external_connection_export[1] => data_flag_rx_external_connection_export[1].IN1
data_flag_rx_external_connection_export[2] => data_flag_rx_external_connection_export[2].IN1
data_flag_rx_external_connection_export[3] => data_flag_rx_external_connection_export[3].IN1
data_flag_rx_external_connection_export[4] => data_flag_rx_external_connection_export[4].IN1
data_flag_rx_external_connection_export[5] => data_flag_rx_external_connection_export[5].IN1
data_flag_rx_external_connection_export[6] => data_flag_rx_external_connection_export[6].IN1
data_flag_rx_external_connection_export[7] => data_flag_rx_external_connection_export[7].IN1
data_flag_rx_external_connection_export[8] => data_flag_rx_external_connection_export[8].IN1
data_info_external_connection_export[0] => data_info_external_connection_export[0].IN1
data_info_external_connection_export[1] => data_info_external_connection_export[1].IN1
data_info_external_connection_export[2] => data_info_external_connection_export[2].IN1
data_info_external_connection_export[3] => data_info_external_connection_export[3].IN1
data_info_external_connection_export[4] => data_info_external_connection_export[4].IN1
data_info_external_connection_export[5] => data_info_external_connection_export[5].IN1
data_info_external_connection_export[6] => data_info_external_connection_export[6].IN1
data_info_external_connection_export[7] => data_info_external_connection_export[7].IN1
data_info_external_connection_export[8] => data_info_external_connection_export[8].IN1
data_info_external_connection_export[9] => data_info_external_connection_export[9].IN1
data_info_external_connection_export[10] => data_info_external_connection_export[10].IN1
data_info_external_connection_export[11] => data_info_external_connection_export[11].IN1
data_info_external_connection_export[12] => data_info_external_connection_export[12].IN1
data_info_external_connection_export[13] => data_info_external_connection_export[13].IN1
data_read_en_rx_external_connection_export <= ulight_fifo_auto_start:data_read_en_rx.out_port
fifo_empty_rx_status_external_connection_export => fifo_empty_rx_status_external_connection_export.IN1
fifo_empty_tx_status_external_connection_export => fifo_empty_tx_status_external_connection_export.IN1
fifo_full_rx_status_external_connection_export => fifo_full_rx_status_external_connection_export.IN1
fifo_full_tx_status_external_connection_export => fifo_full_tx_status_external_connection_export.IN1
fsm_info_external_connection_export[0] => fsm_info_external_connection_export[0].IN1
fsm_info_external_connection_export[1] => fsm_info_external_connection_export[1].IN1
fsm_info_external_connection_export[2] => fsm_info_external_connection_export[2].IN1
fsm_info_external_connection_export[3] => fsm_info_external_connection_export[3].IN1
fsm_info_external_connection_export[4] => fsm_info_external_connection_export[4].IN1
fsm_info_external_connection_export[5] => fsm_info_external_connection_export[5].IN1
led_pio_test_external_connection_export[0] <= ulight_fifo_led_pio_test:led_pio_test.out_port
led_pio_test_external_connection_export[1] <= ulight_fifo_led_pio_test:led_pio_test.out_port
led_pio_test_external_connection_export[2] <= ulight_fifo_led_pio_test:led_pio_test.out_port
led_pio_test_external_connection_export[3] <= ulight_fifo_led_pio_test:led_pio_test.out_port
led_pio_test_external_connection_export[4] <= ulight_fifo_led_pio_test:led_pio_test.out_port
link_disable_external_connection_export <= ulight_fifo_auto_start:link_disable.out_port
link_start_external_connection_export <= ulight_fifo_auto_start:link_start.out_port
memory_mem_a[0] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[1] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[2] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[3] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[4] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[5] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[6] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[7] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[8] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[9] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[10] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[11] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_a[12] <= ulight_fifo_hps_0:hps_0.mem_a
memory_mem_ba[0] <= ulight_fifo_hps_0:hps_0.mem_ba
memory_mem_ba[1] <= ulight_fifo_hps_0:hps_0.mem_ba
memory_mem_ba[2] <= ulight_fifo_hps_0:hps_0.mem_ba
memory_mem_ck <= ulight_fifo_hps_0:hps_0.mem_ck
memory_mem_ck_n <= ulight_fifo_hps_0:hps_0.mem_ck_n
memory_mem_cke <= ulight_fifo_hps_0:hps_0.mem_cke
memory_mem_cs_n <= ulight_fifo_hps_0:hps_0.mem_cs_n
memory_mem_ras_n <= ulight_fifo_hps_0:hps_0.mem_ras_n
memory_mem_cas_n <= ulight_fifo_hps_0:hps_0.mem_cas_n
memory_mem_we_n <= ulight_fifo_hps_0:hps_0.mem_we_n
memory_mem_reset_n <= ulight_fifo_hps_0:hps_0.mem_reset_n
memory_mem_dq[0] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[1] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[2] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[3] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[4] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[5] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[6] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dq[7] <> ulight_fifo_hps_0:hps_0.mem_dq
memory_mem_dqs <> ulight_fifo_hps_0:hps_0.mem_dqs
memory_mem_dqs_n <> ulight_fifo_hps_0:hps_0.mem_dqs_n
memory_mem_odt <= ulight_fifo_hps_0:hps_0.mem_odt
memory_mem_dm <= ulight_fifo_hps_0:hps_0.mem_dm
memory_oct_rzqin => memory_oct_rzqin.IN1
pll_0_locked_export <= ulight_fifo_pll_0:pll_0.locked
pll_0_outclk0_clk <= ulight_fifo_pll_0:pll_0.outclk_0
reset_reset_n => _.IN1
reset_reset_n => _.IN1
timecode_ready_rx_external_connection_export => timecode_ready_rx_external_connection_export.IN1
timecode_rx_external_connection_export[0] => timecode_rx_external_connection_export[0].IN1
timecode_rx_external_connection_export[1] => timecode_rx_external_connection_export[1].IN1
timecode_rx_external_connection_export[2] => timecode_rx_external_connection_export[2].IN1
timecode_rx_external_connection_export[3] => timecode_rx_external_connection_export[3].IN1
timecode_rx_external_connection_export[4] => timecode_rx_external_connection_export[4].IN1
timecode_rx_external_connection_export[5] => timecode_rx_external_connection_export[5].IN1
timecode_rx_external_connection_export[6] => timecode_rx_external_connection_export[6].IN1
timecode_rx_external_connection_export[7] => timecode_rx_external_connection_export[7].IN1
timecode_tx_data_external_connection_export[0] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[1] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[2] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[3] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[4] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[5] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[6] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_data_external_connection_export[7] <= ulight_fifo_timecode_tx_data:timecode_tx_data.out_port
timecode_tx_enable_external_connection_export <= ulight_fifo_auto_start:timecode_tx_enable.out_port
timecode_tx_ready_external_connection_export => timecode_tx_ready_external_connection_export.IN1
write_data_fifo_tx_external_connection_export[0] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[1] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[2] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[3] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[4] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[5] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[6] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[7] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_data_fifo_tx_external_connection_export[8] <= ulight_fifo_write_data_fifo_tx:write_data_fifo_tx.out_port
write_en_tx_external_connection_export <= ulight_fifo_auto_start:write_en_tx.out_port


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~
out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= <GND>
readdata[2] <= <GND>
readdata[3] <= <GND>
readdata[4] <= <GND>
readdata[5] <= <GND>
readdata[6] <= <GND>
readdata[7] <= <GND>
readdata[8] <= <GND>
readdata[9] <= <GND>
readdata[10] <= <GND>
readdata[11] <= <GND>
readdata[12] <= <GND>
readdata[13] <= <GND>
readdata[14] <= <GND>
readdata[15] <= <GND>
readdata[16] <= <GND>
readdata[17] <= <GND>
readdata[18] <= <GND>
readdata[19] <= <GND>
readdata[20] <= <GND>
readdata[21] <= <GND>
readdata[22] <= <GND>
readdata[23] <= <GND>
readdata[24] <= <GND>
readdata[25] <= <GND>
readdata[26] <= <GND>
readdata[27] <= <GND>
readdata[28] <= <GND>
readdata[29] <= <GND>
readdata[30] <= <GND>
readdata[31] <= <GND>


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out[0].CLK
clk => data_out[1].CLK
clk => data_out[2].CLK
reset_n => data_out[0].ACLR
reset_n => data_out[1].ACLR
reset_n => data_out[2].ACLR
write_n => always0.IN1
writedata[0] => data_out[0].DATAIN
writedata[1] => data_out[1].DATAIN
writedata[2] => data_out[2].DATAIN
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~
out_port[0] <= data_out[0].DB_MAX_OUTPUT_PORT_TYPE
out_port[1] <= data_out[1].DB_MAX_OUTPUT_PORT_TYPE
out_port[2] <= data_out[2].DB_MAX_OUTPUT_PORT_TYPE
readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= <GND>
readdata[4] <= <GND>
readdata[5] <= <GND>
readdata[6] <= <GND>
readdata[7] <= <GND>
readdata[8] <= <GND>
readdata[9] <= <GND>
readdata[10] <= <GND>
readdata[11] <= <GND>
readdata[12] <= <GND>
readdata[13] <= <GND>
readdata[14] <= <GND>
readdata[15] <= <GND>
readdata[16] <= <GND>
readdata[17] <= <GND>
readdata[18] <= <GND>
readdata[19] <= <GND>
readdata[20] <= <GND>
readdata[21] <= <GND>
readdata[22] <= <GND>
readdata[23] <= <GND>
readdata[24] <= <GND>
readdata[25] <= <GND>
readdata[26] <= <GND>
readdata[27] <= <GND>
readdata[28] <= <GND>
readdata[29] <= <GND>
readdata[30] <= <GND>
readdata[31] <= <GND>


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port[0] => read_mux_out[0].IN1
in_port[1] => read_mux_out[1].IN1
in_port[2] => read_mux_out[2].IN1
in_port[3] => read_mux_out[3].IN1
in_port[4] => read_mux_out[4].IN1
in_port[5] => read_mux_out[5].IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port[0] => read_mux_out[0].IN1
in_port[1] => read_mux_out[1].IN1
in_port[2] => read_mux_out[2].IN1
in_port[3] => read_mux_out[3].IN1
in_port[4] => read_mux_out[4].IN1
in_port[5] => read_mux_out[5].IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port[0] => read_mux_out[0].IN1
in_port[1] => read_mux_out[1].IN1
in_port[2] => read_mux_out[2].IN1
in_port[3] => read_mux_out[3].IN1
in_port[4] => read_mux_out[4].IN1
in_port[5] => read_mux_out[5].IN1
in_port[6] => read_mux_out[6].IN1
in_port[7] => read_mux_out[7].IN1
in_port[8] => read_mux_out[8].IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port[0] => read_mux_out[0].IN1
in_port[1] => read_mux_out[1].IN1
in_port[2] => read_mux_out[2].IN1
in_port[3] => read_mux_out[3].IN1
in_port[4] => read_mux_out[4].IN1
in_port[5] => read_mux_out[5].IN1
in_port[6] => read_mux_out[6].IN1
in_port[7] => read_mux_out[7].IN1
in_port[8] => read_mux_out[8].IN1
in_port[9] => read_mux_out[9].IN1
in_port[10] => read_mux_out[10].IN1
in_port[11] => read_mux_out[11].IN1
in_port[12] => read_mux_out[12].IN1
in_port[13] => read_mux_out[13].IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx
address[0] => Equal0.IN31
address[1] => Equal0.IN30
chipselect => always0.IN0
clk => data_out.CLK
reset_n => data_out.ACLR
write_n => always0.IN1
writedata[0] => data_out.DATAIN
writedata[1] => ~NO_FANOUT~
writedata[2] => ~NO_FANOUT~
writedata[3] => ~NO_FANOUT~
writedata[4] => ~NO_FANOUT~
writedata[5] => ~NO_FANOUT~
writedata[6] => ~NO_FANOUT~
writedata[7] => ~NO_FANOUT~
writedata[8] => ~NO_FANOUT~
writedata[9] => ~NO_FANOUT~
writedata[10] => ~NO_FANOUT~
writedata[11] => ~NO_FANOUT~
writedata[12] => ~NO_FANOUT~
writedata[13] => ~NO_FANOUT~
writedata[14] => ~NO_FANOUT~
writedata[15] => ~NO_FANOUT~
writedata[16] => ~NO_FANOUT~
writedata[17] => ~NO_FANOUT~
writedata[18] => ~NO_FANOUT~
writedata[19] => ~NO_FANOUT~
writedata[20] => ~NO_FANOUT~
writedata[21] => ~NO_FANOUT~
writedata[22] => ~NO_FANOUT~
writedata[23] => ~NO_FANOUT~
writedata[24] => ~NO_FANOUT~
writedata[25] => ~NO_FANOUT~
writedata[26] => ~NO_FANOUT~
writedata[27] => ~NO_FANOUT~
writedata[28] => ~NO_FANOUT~
writedata[29] => ~NO_FANOUT~
writedata[30] => ~NO_FANOUT~
writedata[31] => ~NO_FANOUT~
out_port <= data_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[0] <= read_mux_out.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= <GND>
readdata[2] <= <GND>
readdata[3] <= <GND>
readdata[4] <= <GND>
readdata[5] <= <GND>
readdata[6] <= <GND>
readdata[7] <= <GND>
readdata[8] <= <GND>
readdata[9] <= <GND>
readdata[10] <= <GND>
readdata[11] <= <GND>
readdata[12] <= <GND>
readdata[13] <= <GND>
readdata[14] <= <GND>
readdata[15] <= <GND>
readdata[16] <= <GND>
readdata[17] <= <GND>
readdata[18] <= <GND>
readdata[19] <= <GND>
readdata[20] <= <GND>
readdata[21] <= <GND>
readdata[22] <= <GND>
readdata[23] <= <GND>
readdata[24] <= <GND>
readdata[25] <= <GND>
readdata[26] <= <GND>
readdata[27] <= <GND>
readdata[28] <= <GND>
readdata[29] <= <GND>
readdata[30] <= <GND>
readdata[31] <= <GND>


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port => read_mux_out.IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port => read_mux_out.IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port => read_mux_out.IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port => read_mux_out.IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info
address[0] => Equal0.IN31
address[1] => Equal0.IN30
clk => readdata[0]~reg0.CLK
clk => readdata[1]~reg0.CLK
clk => readdata[2]~reg0.CLK
clk => readdata[3]~reg0.CLK
clk => readdata[4]~reg0.CLK
clk => readdata[5]~reg0.CLK
clk => readdata[6]~reg0.CLK
clk => readdata[7]~reg0.CLK
clk => readdata[8]~reg0.CLK
clk => readdata[9]~reg0.CLK
clk => readdata[10]~reg0.CLK
clk => readdata[11]~reg0.CLK
clk => readdata[12]~reg0.CLK
clk => readdata[13]~reg0.CLK
clk => readdata[14]~reg0.CLK
clk => readdata[15]~reg0.CLK
clk => readdata[16]~reg0.CLK
clk => readdata[17]~reg0.CLK
clk => readdata[18]~reg0.CLK
clk => readdata[19]~reg0.CLK
clk => readdata[20]~reg0.CLK
clk => readdata[21]~reg0.CLK
clk => readdata[22]~reg0.CLK
clk => readdata[23]~reg0.CLK
clk => readdata[24]~reg0.CLK
clk => readdata[25]~reg0.CLK
clk => readdata[26]~reg0.CLK
clk => readdata[27]~reg0.CLK
clk => readdata[28]~reg0.CLK
clk => readdata[29]~reg0.CLK
clk => readdata[30]~reg0.CLK
clk => readdata[31]~reg0.CLK
in_port[0] => read_mux_out[0].IN1
in_port[1] => read_mux_out[1].IN1
in_port[2] => read_mux_out[2].IN1
in_port[3] => read_mux_out[3].IN1
in_port[4] => read_mux_out[4].IN1
in_port[5] => read_mux_out[5].IN1
reset_n => readdata[0]~reg0.ACLR
reset_n => readdata[1]~reg0.ACLR
reset_n => readdata[2]~reg0.ACLR
reset_n => readdata[3]~reg0.ACLR
reset_n => readdata[4]~reg0.ACLR
reset_n => readdata[5]~reg0.ACLR
reset_n => readdata[6]~reg0.ACLR
reset_n => readdata[7]~reg0.ACLR
reset_n => readdata[8]~reg0.ACLR
reset_n => readdata[9]~reg0.ACLR
reset_n => readdata[10]~reg0.ACLR
reset_n => readdata[11]~reg0.ACLR
reset_n => readdata[12]~reg0.ACLR
reset_n => readdata[13]~reg0.ACLR
reset_n => readdata[14]~reg0.ACLR
reset_n => readdata[15]~reg0.ACLR
reset_n => readdata[16]~reg0.ACLR
reset_n => readdata[17]~reg0.ACLR
reset_n => readdata[18]~reg0.ACLR
reset_n => readdata[19]~reg0.ACLR
reset_n => readdata[20]~reg0.ACLR
reset_n => readdata[21]~reg0.ACLR
reset_n => readdata[22]~reg0.ACLR
reset_n => readdata[23]~reg0.ACLR
reset_n => readdata[24]~reg0.ACLR
reset_n => readdata[25]~reg0.ACLR
reset_n => readdata[26]~reg0.ACLR
reset_n => readdata[27]~reg0.ACLR
reset_n => readdata[28]~reg0.ACLR
reset_n => readdata[29]~reg0.ACLR
reset_n => readdata[30]~reg0.ACLR
reset_n => readdata[31]~reg0.ACLR
readdata[0] <= readdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[1] <= readdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[2] <= readdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[3] <= readdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[4] <= readdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[5] <= readdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[6] <= readdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[7] <= readdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[8] <= readdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[9] <= readdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[10] <= readdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[11] <= readdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[12] <= readdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[13] <= readdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[14] <= readdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[15] <= readdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[16] <= readdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[17] <= readdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[18] <= readdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[19] <= readdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[20] <= readdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[21] <= readdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[22] <= readdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[23] <= readdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[24] <= readdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[25] <= readdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[26] <= readdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[27] <= readdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[28] <= readdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[29] <= readdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[30] <= readdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
readdata[31] <= readdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0
h2f_rst_n <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_rst_n
h2f_axi_clk => h2f_axi_clk.IN1
h2f_AWID[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWID[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWID
h2f_AWADDR[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[12] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[13] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[14] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[15] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[16] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[17] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[18] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[19] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[20] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[21] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[22] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[23] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[24] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[25] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[26] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[27] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[28] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWADDR[29] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWADDR
h2f_AWLEN[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLEN
h2f_AWLEN[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLEN
h2f_AWLEN[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLEN
h2f_AWLEN[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLEN
h2f_AWSIZE[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWSIZE
h2f_AWSIZE[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWSIZE
h2f_AWSIZE[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWSIZE
h2f_AWBURST[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWBURST
h2f_AWBURST[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWBURST
h2f_AWLOCK[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLOCK
h2f_AWLOCK[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWLOCK
h2f_AWCACHE[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWCACHE
h2f_AWCACHE[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWCACHE
h2f_AWCACHE[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWCACHE
h2f_AWCACHE[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWCACHE
h2f_AWPROT[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWPROT
h2f_AWPROT[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWPROT
h2f_AWPROT[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWPROT
h2f_AWVALID <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_AWVALID
h2f_AWREADY => h2f_AWREADY.IN1
h2f_WID[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WID[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WID
h2f_WDATA[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[12] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[13] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[14] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[15] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[16] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[17] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[18] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[19] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[20] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[21] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[22] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[23] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[24] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[25] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[26] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[27] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[28] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[29] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[30] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WDATA[31] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WDATA
h2f_WSTRB[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WSTRB
h2f_WSTRB[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WSTRB
h2f_WSTRB[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WSTRB
h2f_WSTRB[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WSTRB
h2f_WLAST <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WLAST
h2f_WVALID <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_WVALID
h2f_WREADY => h2f_WREADY.IN1
h2f_BID[0] => h2f_BID[0].IN1
h2f_BID[1] => h2f_BID[1].IN1
h2f_BID[2] => h2f_BID[2].IN1
h2f_BID[3] => h2f_BID[3].IN1
h2f_BID[4] => h2f_BID[4].IN1
h2f_BID[5] => h2f_BID[5].IN1
h2f_BID[6] => h2f_BID[6].IN1
h2f_BID[7] => h2f_BID[7].IN1
h2f_BID[8] => h2f_BID[8].IN1
h2f_BID[9] => h2f_BID[9].IN1
h2f_BID[10] => h2f_BID[10].IN1
h2f_BID[11] => h2f_BID[11].IN1
h2f_BRESP[0] => h2f_BRESP[0].IN1
h2f_BRESP[1] => h2f_BRESP[1].IN1
h2f_BVALID => h2f_BVALID.IN1
h2f_BREADY <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_BREADY
h2f_ARID[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARID[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARID
h2f_ARADDR[0] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[1] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[2] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[3] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[4] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[5] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[6] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[7] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[8] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[9] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[10] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[11] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[12] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[13] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[14] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[15] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[16] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR
h2f_ARADDR[17] <= ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces.h2f_ARADDR