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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [spw_fifo_ulight.map.qmsg] - Rev 40
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517798813318 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:46:52 2018 " "Processing started: Mon Feb 5 00:46:52 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813386 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813387 ""}{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "High Performance Effort timing performance increased compilation time " "High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time" { { "Info" "IQCU_OPT_MODE_OVERRIDE" "Fitter Effort Standard Fit " "Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} { "Info" "IQCU_OPT_MODE_OVERRIDE" "Physical Synthesis Effort Level Normal " "Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798823446 ""}{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fsm_m " "Found entity 1: tx_fsm_m" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841413 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841413 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_send " "Found entity 1: tx_fct_send" { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841447 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_counter " "Found entity 1: tx_fct_counter" { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841449 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841449 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_data_send " "Found entity 1: tx_data_send" { } { { "../../rtl/RTL_VB/tx_data_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841459 ""}{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "dont_replicate rx_data_receive.v(64) " "Verilog HDL Attribute warning at rx_data_receive.v(64): overriding existing value for attribute \"dont_replicate\"" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 64 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_receive " "Found entity 1: rx_data_receive" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_control_p " "Found entity 1: rx_data_control_p" { } { { "../../rtl/RTL_VB/rx_data_control_p.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841474 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_buffer_data_w " "Found entity 1: rx_data_buffer_data_w" { } { { "../../rtl/RTL_VB/rx_data_buffer_data_w.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841476 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_control_data_rdy " "Found entity 1: rx_control_data_rdy" { } { { "../../rtl/RTL_VB/rx_control_data_rdy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841477 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841477 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_buffer_fsm " "Found entity 1: rx_buffer_fsm" { } { { "../../rtl/RTL_VB/rx_buffer_fsm.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841480 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841480 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 mem_data " "Found entity 1: mem_data" { } { { "../../rtl/RTL_VB/mem_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841491 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841491 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_neg " "Found entity 1: counter_neg" { } { { "../../rtl/RTL_VB/counter_neg.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841493 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_control " "Found entity 1: bit_capture_control" { } { { "../../rtl/RTL_VB/bitc_capture_control.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841496 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841496 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_data " "Found entity 1: bit_capture_data" { } { { "../../rtl/RTL_VB/bit_capture_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841498 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841513 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841515 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841526 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841537 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841540 ""}{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(43) " "Verilog HDL Attribute warning at fifo_tx.v(43): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 43 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""}{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(44) " "Verilog HDL Attribute warning at fifo_tx.v(44): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 44 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841557 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841565 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../../rtl/DEBUG_VERILOG/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841587 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841587 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841619 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841619 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../../rtl/DEBUG_VERILOG/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841635 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841654 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841654 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841669 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841685 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841728 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841728 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841730 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841730 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841757 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841757 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841760 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841760 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841761 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841806 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841849 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841849 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841860 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841909 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841909 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841922 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841922 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841929 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841949 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841950 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841950 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841952 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841954 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841955 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841956 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841959 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841959 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841960 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841997 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841997 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842043 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842043 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842045 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842087 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842140 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""}{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842184 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842230 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842230 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842266 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842266 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842284 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842287 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842330 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842341 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842342 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842343 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842388 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842446 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842447 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842457 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842467 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842650 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842667 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842667 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842676 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842685 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842686 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842686 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842687 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842687 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842699 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842699 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842714 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842714 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842715 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842715 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842717 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842717 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842719 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842719 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842721 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842721 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842740 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842752 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842809 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842822 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842822 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842828 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842830 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842830 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842834 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842834 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842842 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842842 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842843 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842843 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842845 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842845 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842846 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842847 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842847 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842850 ""}{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(99) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(99): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 99 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""}{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1517798843221 ""}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843242 "|SPW_ULIGHT_FIFO"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843245 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843262 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843287 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843332 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843346 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843368 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843383 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843418 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843456 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843552 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843603 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843672 ""}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843696 ""}{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843710 ""}{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798843726 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"}{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_