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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [db/] [spw_fifo_ulight.sta.qmsg] - Rev 32
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1503625289061 ""}{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1503625289082 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 24 22:41:25 2017 " "Processing started: Thu Aug 24 22:41:25 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1503625289082 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625289082 ""}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625289083 ""}{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625289199 ""}{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625290647 ""}{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625290647 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625290700 ""}{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625290701 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625290840 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625298992 ""}{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625299858 ""}{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625299933 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625299990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625299990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -11503625299990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625299990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625299990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625299990 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625299990 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300124 ""}{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625300322 ""}{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625300346 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.403 " "Worst-case setup slack is 1.403" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300537 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.403 0.000 FPGA_CLK1_50 " " 1.403 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300537 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300537 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.221 " "Worst-case hold slack is 0.221" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300572 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300572 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.221 0.000 FPGA_CLK1_50 " " 0.221 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300572 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300572 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.786 " "Worst-case recovery slack is 4.786" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300586 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.786 0.000 FPGA_CLK1_50 " " 4.786 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300586 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300586 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.870 " "Worst-case removal slack is 0.870" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.870 0.000 FPGA_CLK1_50 " " 0.870 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300602 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300602 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.338 " "Worst-case minimum pulse width slack is 0.338" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.338 0.000 din_a " " 0.338 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.512 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.512 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.537 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.537 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.797 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.797 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.202 0.000 FPGA_CLK1_50 " " 4.202 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625300606 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300606 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.014 ns " "Worst Case Available Settling Time: 11.014 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625300677 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300677 ""}{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625300685 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625300887 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625307671 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625308093 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625308093 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -11503625308093 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625308093 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625308093 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625308093 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308093 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308196 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.581 " "Worst-case setup slack is 1.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308531 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.581 0.000 FPGA_CLK1_50 " " 1.581 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308531 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308531 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.200 " "Worst-case hold slack is 0.200" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308572 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308572 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.200 0.000 FPGA_CLK1_50 " " 0.200 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308572 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308572 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.853 " "Worst-case recovery slack is 4.853" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308587 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308587 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.853 0.000 FPGA_CLK1_50 " " 4.853 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308587 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308587 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.822 " "Worst-case removal slack is 0.822" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308605 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.822 0.000 FPGA_CLK1_50 " " 0.822 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308605 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308605 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.332 " "Worst-case minimum pulse width slack is 0.332" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.332 0.000 din_a " " 0.332 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.464 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.464 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.580 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.580 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.801 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.801 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.284 0.000 FPGA_CLK1_50 " " 4.284 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625308609 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308609 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 11.260 ns " "Worst Case Available Settling Time: 11.260 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625308653 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308653 ""}{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625308660 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625308987 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316048 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625316472 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625316472 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -11503625316472 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625316472 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625316472 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625316472 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316472 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316571 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.677 " "Worst-case setup slack is 4.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316804 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316804 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.677 0.000 FPGA_CLK1_50 " " 4.677 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316804 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316804 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.137 " "Worst-case hold slack is 0.137" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316841 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.137 0.000 FPGA_CLK1_50 " " 0.137 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316841 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316841 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.858 " "Worst-case recovery slack is 6.858" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316853 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316853 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.858 0.000 FPGA_CLK1_50 " " 6.858 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316853 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316853 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.501 " "Worst-case removal slack is 0.501" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316865 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.501 0.000 FPGA_CLK1_50 " " 0.501 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316865 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316865 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.364 " "Worst-case minimum pulse width slack is 0.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.497 0.000 din_a " " 0.497 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.759 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.759 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.799 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.799 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.029 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 1.029 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.076 0.000 FPGA_CLK1_50 " " 4.076 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625316870 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316870 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.118 ns " "Worst Case Available Settling Time: 14.118 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625316914 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625316914 ""}{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1503625316922 ""}{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625317149 ""}{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625323670 ""}{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625324100 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625324100 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -11503625324100 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625324100 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625324100 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1503625324100 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324100 ""}{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324198 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.192 " "Worst-case setup slack is 5.192" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324442 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.192 0.000 FPGA_CLK1_50 " " 5.192 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324442 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324442 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.122 " "Worst-case hold slack is 0.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.122 0.000 FPGA_CLK1_50 " " 0.122 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324478 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324478 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 7.031 " "Worst-case recovery slack is 7.031" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324495 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.031 0.000 FPGA_CLK1_50 " " 7.031 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324495 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324495 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.453 " "Worst-case removal slack is 0.453" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324511 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.453 0.000 FPGA_CLK1_50 " " 0.453 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324511 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324511 ""}{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.364 " "Worst-case minimum pulse width slack is 0.364" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.364 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.599 0.000 din_a " " 0.599 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.792 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.792 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.860 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.860 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.057 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 1.057 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.039 0.000 FPGA_CLK1_50 " " 4.039 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1503625324515 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324515 ""}{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.664 ns " "Worst Case Available Settling Time: 14.664 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1503625324561 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625324561 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625325853 ""}{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625325853 ""}{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1351 " "Peak virtual memory: 1351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1503625326013 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 24 22:42:06 2017 " "Processing ended: Thu Aug 24 22:42:06 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1503625326013 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:41 " "Elapsed time: 00:00:41" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1503625326013 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:57 " "Total CPU time (on all processors): 00:00:57" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1503625326013 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1503625326013 ""}
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