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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.asm.rpt] - Rev 32
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Assembler report for spw_fifo_ulightThu Aug 24 22:41:24 2017Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Assembler Summary3. Assembler Settings4. Assembler Generated Files5. Assembler Device Options: spw_fifo_ulight.sof6. Assembler Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel MegaCore Function License Agreement, or otherapplicable license agreement, including, without limitation,that your use is for the sole purpose of programming logicdevices manufactured by Intel and sold by Intel or itsauthorized distributors. Please refer to the applicableagreement for further details.+---------------------------------------------------------------+; Assembler Summary ;+-----------------------+---------------------------------------+; Assembler Status ; Successful - Thu Aug 24 22:41:24 2017 ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Device ; 5CSEMA4U23C6 ;+-----------------------+---------------------------------------++----------------------------------+; Assembler Settings ;+--------+---------+---------------+; Option ; Setting ; Default Value ;+--------+---------+---------------++---------------------------------------------------------------------------------------------------------------------------------------+; Assembler Generated Files ;+---------------------------------------------------------------------------------------------------------------------------------------+; File Name ;+---------------------------------------------------------------------------------------------------------------------------------------+; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.sof ;+---------------------------------------------------------------------------------------------------------------------------------------++-----------------------------------------------+; Assembler Device Options: spw_fifo_ulight.sof ;+----------------+------------------------------+; Option ; Setting ;+----------------+------------------------------+; JTAG usercode ; 0x00AD1064 ;; Checksum ; 0x00AD1064 ;+----------------+------------------------------++--------------------+; Assembler Messages ;+--------------------+Info: *******************************************************************Info: Running Quartus Prime AssemblerInfo: Version 17.0.1 Build 598 06/07/2017 SJ Lite EditionInfo: Processing started: Thu Aug 24 22:41:08 2017Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulightWarning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (115030): Assembler is generating device programming filesInfo (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not requiredInfo: Quartus Prime Assembler was successful. 0 errors, 1 warningInfo: Peak virtual memory: 1026 megabytesInfo: Processing ended: Thu Aug 24 22:41:24 2017Info: Elapsed time: 00:00:16Info: Total CPU time (on all processors): 00:00:10
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