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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.fit.rpt] - Rev 40
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Fitter report for spw_fifo_ulightMon Feb 5 00:57:17 2018Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. Parallel Compilation5. Fitter Netlist Optimizations6. Ignored Assignments7. Incremental Compilation Preservation Summary8. Incremental Compilation Partition Settings9. Incremental Compilation Placement Preservation10. Pin-Out File11. Fitter Resource Usage Summary12. Fitter Partition Statistics13. Input Pins14. Output Pins15. I/O Bank Usage16. All Package Pins17. I/O Assignment Warnings18. PLL Usage Summary19. Fitter Resource Utilization by Entity20. Delay Chain Summary21. Pad To Core Delay Chain Fanout22. Control Signals23. Global & Other Fast Signals24. Non-Global High Fan-Out Signals25. Routing Usage Summary26. I/O Rules Summary27. I/O Rules Details28. I/O Rules Matrix29. Fitter Device Options30. Operating Settings and Conditions31. Estimated Delay Added for Hold Timing Summary32. Estimated Delay Added for Hold Timing Details33. Fitter Messages34. Fitter Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details.+----------------------------------------------------------------------------------------+; Fitter Summary ;+---------------------------------+------------------------------------------------------+; Fitter Status ; Successful - Mon Feb 5 00:57:17 2018 ;; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;; Revision Name ; spw_fifo_ulight ;; Top-level Entity Name ; SPW_ULIGHT_FIFO ;; Family ; Cyclone V ;; Device ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;; Total registers ; 4633 ;; Total pins ; 19 / 314 ( 6 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;; Total RAM Blocks ; 0 / 270 ( 0 % ) ;; Total DSP Blocks ; 0 / 84 ( 0 % ) ;; Total HSSI RX PCSs ; 0 ;; Total HSSI PMA RX Deserializers ; 0 ;; Total HSSI TX PCSs ; 0 ;; Total HSSI PMA TX Serializers ; 0 ;; Total PLLs ; 1 / 5 ( 20 % ) ;; Total DLLs ; 0 / 4 ( 0 % ) ;+---------------------------------+------------------------------------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Option ; Setting ; Default Value ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+; Device ; 5CSEMA4U23C6 ; ;; Minimum Core Junction Temperature ; 0 ; ;; Maximum Core Junction Temperature ; 85 ; ;; Router Timing Optimization Level ; MAXIMUM ; Normal ;; Placement Effort Multiplier ; 4.0 ; 1.0 ;; Auto RAM to MLAB Conversion ; Off ; On ;; Power Optimization During Fitting ; Extra effort ; Normal compilation ;; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ;; Auto Delay Chains for High Fanout Input Pins ; On ; Off ;; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;; Perform Asynchronous Signal Pipelining ; On ; Off ;; Physical Synthesis Effort Level ; Extra ; Normal ;; Logic Cell Insertion - Logic Duplication ; Off ; Auto ;; Auto Register Duplication ; Off ; Auto ;; Optimize Design for Metastability ; Off ; On ;; Use smart compilation ; Off ; Off ;; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;; Enable compact report table ; Off ; Off ;; Perform Clocking Topology Analysis During Routing ; Off ; Off ;; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;; Optimize Hold Timing ; All Paths ; All Paths ;; Optimize Multi-Corner Timing ; On ; On ;; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;; SSN Optimization ; Off ; Off ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize Timing for ECOs ; Off ; Off ;; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; Periphery to Core Placement and Routing Optimization ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Packed Registers ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Treat Bidirectional Pin as Output Pin ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;; Synchronizer Identification ; Auto ; Auto ;; Enable Beneficial Skew Optimization ; On ; On ;; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;; Clamping Diode ; Off ; Off ;; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;; Advanced Physical Optimization ; On ; On ;+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.09 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 9.1% ;+----------------------------+-------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Netlist Optimizations ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~41 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add1~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1_RESYN160_BDD161 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_RESYN126_BDD127 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_RESYN148_BDD149 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_RESYN150_BDD151 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_RESYN152_BDD153 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN138_BDD139 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN140_BDD141 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~53 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~56 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~66 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97_RESYN164_BDD165 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98_RESYN166_BDD167 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~99 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100_RESYN168_BDD169 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; debounce_db:db_system_spwulight_b|Add0~62 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; debounce_db:db_system_spwulight_b|counter~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~1_RESYN162_BDD163 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|always5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1_RESYN170_BDD171 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add7~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Selector18~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|rd_ptr~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add1~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add2~26 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6_RESYN58_BDD59 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7_RESYN60_BDD61 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8_RESYN62_BDD63 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9_RESYN64_BDD65 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10_RESYN66_BDD67 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11_RESYN68_BDD69 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12_RESYN70_BDD71 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|always2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13_RESYN72_BDD73 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1_RESYN104_BDD105 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1_RESYN154_BDD155 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1_RESYN156_BDD157 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0_RESYN158_BDD159 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Equal4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1_RESYN128_BDD129 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ShiftRight1~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4_RESYN146_BDD147 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~15 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~8 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18_RESYN130_BDD131 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN132_BDD133 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN134_BDD135 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25_RESYN136_BDD137 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~28 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1_RESYN120_BDD121 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3_RESYN122_BDD123 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4_RESYN124_BDD125 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1_RESYN142_BDD143 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0_RESYN144_BDD145 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3_RESYN76_BDD77 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5_RESYN78_BDD79 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10_RESYN80_BDD81 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9_RESYN98_BDD99 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10_RESYN100_BDD101 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN108_BDD109 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN110_BDD111 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13_RESYN112_BDD113 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14_RESYN114_BDD115 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3_RESYN84_BDD85 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[0]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[1]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[2]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[3]~output ; I ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4]~_Duplicate_1 ; Q ; ;; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[4]~output ; I ; ;+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------++---------------------------------------------------------------------------------------------+; Ignored Assignments ;+--------------+-----------------+--------------+------------+---------------+----------------+; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;+--------------+-----------------+--------------+------------+---------------+----------------+; I/O Standard ; SPW_ULIGHT_FIFO ; ; KEY ; 3.3-V LVTTL ; QSF Assignment ;; I/O Standard ; SPW_ULIGHT_FIFO ; ; LED ; 3.3-V LVTTL ; QSF Assignment ;+--------------+-----------------+--------------+------------+---------------+----------------++----------------------------------------------------------------------------------------------------+; Incremental Compilation Preservation Summary ;+---------------------+----------------------+----------------------------+--------------------------+; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;+---------------------+----------------------+----------------------------+--------------------------+; Placement (by node) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;; -- Achieved ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ;; ; ; ; ;; Routing (by net) ; ; ; ;; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;+---------------------+----------------------+----------------------------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Partition Settings ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------++------------------------------------------------------------------------------------------------------------------------------------+; Incremental Compilation Placement Preservation ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+; Top ; 0.00 % ( 0 / 10065 ) ; N/A ; Source File ; N/A ; ;; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ;+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------++--------------+; Pin-Out File ;+--------------+The pin-out file can be found in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.pin.+---------------------------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+-------------------------------------------------------------+-----------------------+-------+; Resource ; Usage ; % ;+-------------------------------------------------------------+-----------------------+-------+; Logic utilization (ALMs needed / total ALMs on device) ; 3,362 / 15,880 ; 21 % ;; ALMs needed [=A-B+C] ; 3,362 ; ;; [A] ALMs used in final placement [=a+b+c+d] ; 3,835 / 15,880 ; 24 % ;; [a] ALMs used for LUT logic and registers ; 1,626 ; ;; [b] ALMs used for LUT logic ; 1,539 ; ;; [c] ALMs used for registers ; 670 ; ;; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15,880 ; 3 % ;; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15,880 ; < 1 % ;; [a] Due to location constrained logic ; 0 ; ;; [b] Due to LAB-wide signal conflicts ; 10 ; ;; [c] Due to LAB input limits ; 6 ; ;; [d] Due to virtual I/Os ; 0 ; ;; ; ; ;; Difficulty packing design ; Low ; ;; ; ; ;; Total LABs: partially or completely used ; 464 / 1,588 ; 29 % ;; -- Logic LABs ; 464 ; ;; -- Memory LABs (up to half of total LABs) ; 0 ; ;; ; ; ;; Combinational ALUT usage for logic ; 5,522 ; ;; -- 7 input functions ; 72 ; ;; -- 6 input functions ; 1,329 ; ;; -- 5 input functions ; 874 ; ;; -- 4 input functions ; 1,532 ; ;; -- <=3 input functions ; 1,715 ; ;; Combinational ALUT usage for route-throughs ; 415 ; ;; ; ; ;; Dedicated logic registers ; 4,628 ; ;; -- By type: ; ; ;; -- Primary logic registers ; 4,592 / 31,760 ; 14 % ;; -- Secondary logic registers ; 36 / 31,760 ; < 1 % ;; -- By function: ; ; ;; -- Design implementation registers ; 4,628 ; ;; -- Routing optimization registers ; 0 ; ;; ; ; ;; Virtual pins ; 0 ; ;; I/O pins ; 19 / 314 ; 6 % ;; -- Clock pins ; 2 / 6 ; 33 % ;; -- Dedicated input pins ; 0 / 21 ; 0 % ;; I/O registers ; 5 ; ;; ; ; ;; Hard processor system peripheral utilization ; ; ;; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ;; -- Clock resets ; 1 / 1 ( 100 % ) ; ;; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;; -- S2F AXI ; 1 / 1 ( 100 % ) ; ;; -- F2S AXI ; 1 / 1 ( 100 % ) ; ;; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;; -- SDRAM ; 1 / 1 ( 100 % ) ; ;; -- Interrupts ; 0 / 1 ( 0 % ) ; ;; -- JTAG ; 0 / 1 ( 0 % ) ; ;; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;; -- STM event ; 0 / 1 ( 0 % ) ; ;; -- TPIU trace ; 1 / 1 ( 100 % ) ; ;; -- DMA ; 0 / 1 ( 0 % ) ; ;; -- CAN ; 0 / 2 ( 0 % ) ; ;; -- EMAC ; 0 / 2 ( 0 % ) ; ;; -- I2C ; 0 / 4 ( 0 % ) ; ;; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;; -- QSPI ; 0 / 1 ( 0 % ) ; ;; -- SDMMC ; 0 / 1 ( 0 % ) ; ;; -- SPI Master ; 0 / 2 ( 0 % ) ; ;; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;; -- UART ; 0 / 2 ( 0 % ) ; ;; -- USB ; 0 / 2 ( 0 % ) ; ;; ; ; ;; M10K blocks ; 0 / 270 ; 0 % ;; Total MLAB memory bits ; 0 ; ;; Total block memory bits ; 0 / 2,764,800 ; 0 % ;; Total block memory implementation bits ; 0 / 2,764,800 ; 0 % ;; ; ; ;; Total DSP Blocks ; 0 / 84 ; 0 % ;; ; ; ;; Fractional PLLs ; 1 / 5 ; 20 % ;; Global signals ; 4 ; ;; -- Global clocks ; 3 / 16 ; 19 % ;; -- Quadrant clocks ; 0 / 72 ; 0 % ;; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ;; SERDES Transmitters ; 0 / 76 ; 0 % ;; SERDES Receivers ; 0 / 76 ; 0 % ;; JTAGs ; 0 / 1 ; 0 % ;; ASMI blocks ; 0 / 1 ; 0 % ;; CRC blocks ; 0 / 1 ; 0 % ;; Remote update blocks ; 0 / 1 ; 0 % ;; Oscillator blocks ; 0 / 1 ; 0 % ;; Impedance control blocks ; 0 / 3 ; 0 % ;; Hard Memory Controllers ; 0 / 2 ; 0 % ;; Average interconnect usage (total/H/V) ; 6.0% / 6.2% / 5.2% ; ;; Peak interconnect usage (total/H/V) ; 26.6% / 28.9% / 23.3% ; ;; Maximum fan-out ; 3073 ; ;; Highest non-global fan-out ; 2974 ; ;; Total fan-out ; 40291 ; ;; Average fan-out ; 3.79 ; ;+-------------------------------------------------------------+-----------------------+-------++---------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Partition Statistics ;+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ;+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+; Logic utilization (ALMs needed / total ALMs on device) ; 3362 / 15880 ( 21 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; ALMs needed [=A-B+C] ; 3362 ; 0 ; 0 ;; [A] ALMs used in final placement [=a+b+c+d] ; 3835 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [a] ALMs used for LUT logic and registers ; 1626 ; 0 ; 0 ;; [b] ALMs used for LUT logic ; 1539 ; 0 ; 0 ;; [c] ALMs used for registers ; 670 ; 0 ; 0 ;; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ;; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15880 ( 3 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ;; [a] Due to location constrained logic ; 0 ; 0 ; 0 ;; [b] Due to LAB-wide signal conflicts ; 10 ; 0 ; 0 ;; [c] Due to LAB input limits ; 6 ; 0 ; 0 ;; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ;; ; ; ; ;; Difficulty packing design ; Low ; Low ; Low ;; ; ; ; ;; Total LABs: partially or completely used ; 464 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ;; -- Logic LABs ; 464 ; 0 ; 0 ;; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ;; ; ; ; ;; Combinational ALUT usage for logic ; 5522 ; 0 ; 0 ;; -- 7 input functions ; 72 ; 0 ; 0 ;; -- 6 input functions ; 1329 ; 0 ; 0 ;; -- 5 input functions ; 874 ; 0 ; 0 ;; -- 4 input functions ; 1532 ; 0 ; 0 ;; -- <=3 input functions ; 1715 ; 0 ; 0 ;; Combinational ALUT usage for route-throughs ; 415 ; 0 ; 0 ;; Memory ALUT usage ; 0 ; 0 ; 0 ;; -- 64-address deep ; 0 ; 0 ; 0 ;; -- 32-address deep ; 0 ; 0 ; 0 ;; ; ; ; ;; Dedicated logic registers ; 0 ; 0 ; 0 ;; -- By type: ; ; ; ;; -- Primary logic registers ; 4592 / 31760 ( 14 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;; -- Secondary logic registers ; 36 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ;; -- By function: ; ; ; ;; -- Design implementation registers ; 4628 ; 0 ; 0 ;; -- Routing optimization registers ; 0 ; 0 ; 0 ;; ; ; ; ;; ; ; ; ;; Virtual pins ; 0 ; 0 ; 0 ;; I/O pins ; 17 ; 0 ; 2 ;; I/O registers ; 5 ; 0 ; 0 ;; Total block memory bits ; 0 ; 0 ; 0 ;; Total block memory implementation bits ; 0 ; 0 ; 0 ;; Clock enable block ; 0 / 110 ( 0 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ;; Double data rate I/O output circuitry ; 5 / 304 ( 1 % ) ; 0 / 304 ( 0 % ) ; 0 / 304 ( 0 % ) ;; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS clock resets interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; FPGA-to-HPS interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS FPGA-to-SDRAM interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS-to-FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; HPS TPIU trace interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ;; PLL Output Counter ; 0 / 45 ( 0 % ) ; 0 / 45 ( 0 % ) ; 1 / 45 ( 2 % ) ;; PLL Reconfiguration Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ;; ; ; ; ;; Connections ; ; ; ;; -- Input Connections ; 4377 ; 0 ; 40 ;; -- Registered Input Connections ; 3099 ; 0 ; 0 ;; -- Output Connections ; 40 ; 0 ; 4377 ;; -- Registered Output Connections ; 1 ; 0 ; 0 ;; ; ; ; ;; Internal Connections ; ; ; ;; -- Total Connections ; 40728 ; 0 ; 4454 ;; -- Registered Connections ; 23593 ; 0 ; 0 ;; ; ; ; ;; External Connections ; ; ; ;; -- Top ; 0 ; 0 ; 4417 ;; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ;; -- hard_block:auto_generated_inst ; 4417 ; 0 ; 0 ;; ; ; ; ;; Partition Interface ; ; ; ;; -- Input Ports ; 5 ; 0 ; 41 ;; -- Output Ports ; 10 ; 0 ; 106 ;; -- Bidir Ports ; 0 ; 0 ; 0 ;; ; ; ; ;; Registered Ports ; ; ; ;; -- Registered Input Ports ; 0 ; 0 ; 0 ;; -- Registered Output Ports ; 0 ; 0 ; 0 ;; ; ; ; ;; Port Connectivity ; ; ; ;; -- Input Ports driven by GND ; 0 ; 0 ; 0 ;; -- Output Ports driven by GND ; 0 ; 0 ; 0 ;; -- Input Ports driven by VCC ; 0 ; 0 ; 0 ;; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ;; -- Input Ports with no Source ; 0 ; 0 ; 0 ;; -- Output Ports with no Source ; 0 ; 0 ; 0 ;; -- Input Ports with no Fanout ; 0 ; 0 ; 0 ;; -- O