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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Rev 40

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Analysis & Synthesis Status : Successful - Mon Feb  5 00:52:09 2018
Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
Revision Name : spw_fifo_ulight
Top-level Entity Name : SPW_ULIGHT_FIFO
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Total registers : 4628
Total pins : 15
Total virtual pins : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI PMA RX Deserializers : 0
Total HSSI TX PCSs : 0
Total HSSI PMA TX Serializers : 0
Total PLLs : 1
Total DLLs : 0

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