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TimeQuest Timing Analyzer report for spw_fifo_ulightMon Feb 5 00:59:04 2018Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition---------------------; Table of Contents ;---------------------1. Legal Notice2. TimeQuest Timing Analyzer Summary3. Parallel Compilation4. SDC File List5. Clocks6. Slow 1100mV 85C Model Fmax Summary7. Timing Closure Recommendations8. Slow 1100mV 85C Model Setup Summary9. Slow 1100mV 85C Model Hold Summary10. Slow 1100mV 85C Model Recovery Summary11. Slow 1100mV 85C Model Removal Summary12. Slow 1100mV 85C Model Minimum Pulse Width Summary13. Slow 1100mV 85C Model Metastability Summary14. Slow 1100mV 0C Model Fmax Summary15. Slow 1100mV 0C Model Setup Summary16. Slow 1100mV 0C Model Hold Summary17. Slow 1100mV 0C Model Recovery Summary18. Slow 1100mV 0C Model Removal Summary19. Slow 1100mV 0C Model Minimum Pulse Width Summary20. Slow 1100mV 0C Model Metastability Summary21. Fast 1100mV 85C Model Setup Summary22. Fast 1100mV 85C Model Hold Summary23. Fast 1100mV 85C Model Recovery Summary24. Fast 1100mV 85C Model Removal Summary25. Fast 1100mV 85C Model Minimum Pulse Width Summary26. Fast 1100mV 85C Model Metastability Summary27. Fast 1100mV 0C Model Setup Summary28. Fast 1100mV 0C Model Hold Summary29. Fast 1100mV 0C Model Recovery Summary30. Fast 1100mV 0C Model Removal Summary31. Fast 1100mV 0C Model Minimum Pulse Width Summary32. Fast 1100mV 0C Model Metastability Summary33. Multicorner Timing Analysis Summary34. Board Trace Model Assignments35. Input Transition Times36. Signal Integrity Metrics (Slow 1100mv 0c Model)37. Signal Integrity Metrics (Slow 1100mv 85c Model)38. Signal Integrity Metrics (Fast 1100mv 0c Model)39. Signal Integrity Metrics (Fast 1100mv 85c Model)40. Setup Transfers41. Hold Transfers42. Recovery Transfers43. Removal Transfers44. Report TCCS45. Report RSKM46. Unconstrained Paths Summary47. Clock Status Summary48. Unconstrained Input Ports49. Unconstrained Output Ports50. Unconstrained Input Ports51. Unconstrained Output Ports52. TimeQuest Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 2017 Intel Corporation. All rights reserved.Your use of Intel Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Intel Program LicenseSubscription Agreement, the Intel Quartus Prime License Agreement,the Intel FPGA IP License Agreement, or other applicable licenseagreement, including, without limitation, that your use is forthe sole purpose of programming logic devices manufactured byIntel and sold by Intel or its authorized distributors. Pleaserefer to the applicable agreement for further details.+--------------------------------------------------------------------------------------+; TimeQuest Timing Analyzer Summary ;+-----------------------+--------------------------------------------------------------+; Quartus Prime Version ; Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;; Timing Analyzer ; TimeQuest ;; Revision Name ; spw_fifo_ulight ;; Device Family ; Cyclone V ;; Device Name ; 5CSEMA4U23C6 ;; Timing Models ; Final ;; Delay Model ; Combined ;; Rise/Fall Delays ; Enabled ;+-----------------------+--------------------------------------------------------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 4 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.17 ;; Maximum used ; 2 ;; ; ;; Usage by Processor ; % Time Used ;; Processor 1 ; 100.0% ;; Processor 2 ; 17.2% ;+----------------------------+-------------++--------------------------------------------------------------------------------------------------+; SDC File List ;+--------------------------------------------------------------+--------+--------------------------+; SDC File Path ; Status ; Read at ;+--------------------------------------------------------------+--------+--------------------------+; sdc/spw_fifo_ulight.out.sdc ; OK ; Mon Feb 5 00:57:55 2018 ;; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Mon Feb 5 00:57:55 2018 ;+--------------------------------------------------------------+--------+--------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clocks ;+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i } ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i } ;; din_a ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { din_a } ;; FPGA_CLK1_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e } ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] ; { u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 16 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin ; { u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] } ;+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------++----------------------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Fmax Summary ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+; 82.1 MHz ; 82.1 MHz ; FPGA_CLK1_50 ; ;; 123.85 MHz ; 123.85 MHz ; din_a ; ;; 127.19 MHz ; 127.19 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; ;; 145.58 MHz ; 145.58 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; ;; 159.54 MHz ; 159.54 MHz ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; ;; 201.09 MHz ; 201.09 MHz ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.----------------------------------; Timing Closure Recommendations ;----------------------------------HTML report is unavailable in plain text report export.+---------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Setup Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.369 ; -113.702 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.697 ; -1112.931 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -3.138 ; -13.527 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.473 ; -27.460 ;; din_a ; -2.037 ; -45.867 ;; FPGA_CLK1_50 ; -1.110 ; -2.017 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Hold Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.322 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.336 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.393 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.470 ; 0.000 ;; din_a ; 0.547 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.624 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++---------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Recovery Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -0.289 ; -4.795 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 5.248 ; 0.000 ;; FPGA_CLK1_50 ; 14.466 ; 0.000 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Removal Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.563 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.308 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.746 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 85C Model Minimum Pulse Width Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.533 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.575 ; 0.000 ;; din_a ; 0.994 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.301 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 3.952 ; 0.000 ;; FPGA_CLK1_50 ; 9.195 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------+-----------------------------------------------; Slow 1100mV 85C Model Metastability Summary ;-----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 49Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 12.091 ns+----------------------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Fmax Summary ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+; Fmax ; Restricted Fmax ; Clock Name ; Note ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+; 84.77 MHz ; 84.77 MHz ; FPGA_CLK1_50 ; ;; 127.58 MHz ; 127.58 MHz ; din_a ; ;; 130.77 MHz ; 130.77 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; ;; 149.1 MHz ; 149.1 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; ;; 159.18 MHz ; 159.18 MHz ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; ;; 205.8 MHz ; 205.8 MHz ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; ;+------------+-----------------+--------------------------------------------------------------------------------------------+------+This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.+---------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Setup Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.207 ; -109.829 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.461 ; -1038.103 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -2.976 ; -12.650 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.359 ; -27.122 ;; din_a ; -1.919 ; -41.436 ;; FPGA_CLK1_50 ; -0.765 ; -1.140 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Hold Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.211 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.325 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.388 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.478 ; 0.000 ;; din_a ; 0.530 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.599 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++---------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Recovery Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -0.346 ; -5.707 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 5.377 ; 0.000 ;; FPGA_CLK1_50 ; 14.772 ; 0.000 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Removal Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.464 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.288 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.777 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++--------------------------------------------------------------------------------------------------------------------+; Slow 1100mV 0C Model Minimum Pulse Width Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.499 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.523 ; 0.000 ;; din_a ; 0.986 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.324 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 3.980 ; 0.000 ;; FPGA_CLK1_50 ; 9.277 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------+----------------------------------------------; Slow 1100mV 0C Model Metastability Summary ;----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 49Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 12.233 ns+---------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Setup Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -2.086 ; -3.029 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -1.935 ; -13.800 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1.826 ; -329.386 ;; din_a ; -1.068 ; -12.429 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -0.558 ; -5.149 ;; FPGA_CLK1_50 ; -0.405 ; -0.405 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Hold Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.122 ; 0.000 ;; FPGA_CLK1_50 ; 0.175 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.179 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.217 ; 0.000 ;; din_a ; 0.242 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.302 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++---------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Recovery Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.648 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 6.842 ; 0.000 ;; FPGA_CLK1_50 ; 16.136 ; 0.000 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Removal Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.424 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.665 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.750 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 85C Model Minimum Pulse Width Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.732 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.833 ; 0.000 ;; din_a ; 1.215 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.480 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 4.240 ; 0.000 ;; FPGA_CLK1_50 ; 9.073 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------+-----------------------------------------------; Fast 1100mV 85C Model Metastability Summary ;-----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 49Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 14.729 ns+---------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Setup Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -1.794 ; -2.071 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -1.717 ; -6.939 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1.507 ; -230.983 ;; din_a ; -0.704 ; -5.641 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -0.395 ; -3.443 ;; FPGA_CLK1_50 ; -0.113 ; -0.113 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Hold Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.104 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.164 ; 0.000 ;; FPGA_CLK1_50 ; 0.166 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.199 ; 0.000 ;; din_a ; 0.208 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.263 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++---------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Recovery Summary ;+--------------------------------------------------------------------------------------------+--------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+--------+---------------+; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.654 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 7.148 ; 0.000 ;; FPGA_CLK1_50 ; 16.628 ; 0.000 ;+--------------------------------------------------------------------------------------------+--------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Removal Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; FPGA_CLK1_50 ; 0.327 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.616 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.684 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------++--------------------------------------------------------------------------------------------------------------------+; Fast 1100mV 0C Model Minimum Pulse Width Summary ;+--------------------------------------------------------------------------------------------+-------+---------------+; Clock ; Slack ; End Point TNS ;+--------------------------------------------------------------------------------------------+-------+---------------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.757 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.823 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ;; din_a ; 1.293 ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.525 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 4.335 ; 0.000 ;; FPGA_CLK1_50 ; 9.039 ; 0.000 ;+--------------------------------------------------------------------------------------------+-------+---------------+----------------------------------------------; Fast 1100mV 0C Model Metastability Summary ;----------------------------------------------The design MTBF is not calculated because there are no specified synchronizers in the design.Number of Synchronizer Chains Found: 49Shortest Synchronizer Chain: 2 RegistersFraction of Chains for which MTBFs Could Not be Calculated: 1.000Worst Case Available Settling Time: 15.223 ns+------------------------------------------------------------------------------------------------------------------------------------------------------------+; Multicorner Timing Analysis Summary ;+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+; Worst-case Slack ; -4.369 ; 0.104 ; -0.346 ; 0.327 ; 0.499 ;; FPGA_CLK1_50 ; -1.110 ; 0.166 ; 14.466 ; 0.327 ; 9.039 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.697 ; 0.164 ; 5.248 ; 0.616 ; 3.952 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.369 ; 0.104 ; N/A ; N/A ; 0.523 ;; din_a ; -2.037 ; 0.208 ; N/A ; N/A ; 0.986 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -3.138 ; 0.263 ; -0.346 ; 0.684 ; 1.301 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.473 ; 0.199 ; N/A ; N/A ; 0.499 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ;; Design-wide TNS ; -1315.504 ; 0.0 ; -5.707 ; 0.0 ; 0.0 ;; FPGA_CLK1_50 ; -2.017 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1112.931 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -113.702 ; 0.000 ; N/A ; N/A ; 0.000 ;; din_a ; -45.867 ; 0.000 ; N/A ; N/A ; 0.000 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -13.527 ; 0.000 ; -5.707 ; 0.000 ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -27.460 ; 0.000 ; N/A ; N/A ; 0.000 ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Board Trace Model Assignments ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; dout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; sout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; LED[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; LED[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;; dout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;; sout_a(n) ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ;+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------++-----------------------------------------------------------------+; Input Transition Times ;+--------------+--------------+-----------------+-----------------+; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;+--------------+--------------+-----------------+-----------------+; KEY[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; FPGA_CLK1_50 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; KEY[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;; din_a ; LVDS ; 2000 ps ; 2000 ps ;; sin_a ; LVDS ; 2000 ps ; 2000 ps ;; din_a(n) ; LVDS ; 2000 ps ; 2000 ps ;; sin_a(n) ; LVDS ; 2000 ps ; 2000 ps ;+--------------+--------------+-----------------+-----------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Slow 1100mv 0c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; dout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Slow 1100mv 85c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ;; dout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Fast 1100mv 0c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; dout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Signal Integrity Metrics (Fast 1100mv 85c Model) ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; dout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;; LED[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;; LED[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ;; LED[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;; dout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;; sout_a(n) ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ;+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Setup Transfers ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ;; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ;; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 34 ; 15 ; 4 ; 90 ;; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 60 ; 0 ; 0 ; 0 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 1600 ; 0 ; 0 ; 0 ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Hold Transfers ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ;; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ;; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ;; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1 ; 0 ; 0 ; 0 ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 34 ; 15 ; 4 ; 90 ;; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 60 ; 0 ; 0 ; 0 ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 1600 ; 0 ; 0 ; 0 ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Recovery Transfers ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 20 ; 0 ; 18 ; 0 ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Removal Transfers ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ;; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ;; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 20 ; 0 ; 18 ; 0 ;+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.---------------; Report TCCS ;---------------No dedicated SERDES Transmitter circuitry present in device or used in design---------------; Report RSKM ;---------------No non-DPA dedicated SERDES Receiver circuitry present in device or used in design+------------------------------------------------+; Unconstrained Paths Summary ;+---------------------------------+-------+------+; Property ; Setup ; Hold ;+---------------------------------+-------+------+; Illegal Clocks ; 0 ; 0 ;; Unconstrained Clocks ; 0 ; 0 ;; Unconstrained Input Ports ; 2 ; 2 ;; Unconstrained Input Port Paths ; 34 ; 34 ;; Unconstrained Output Ports ; 10 ; 10 ;; Unconstrained Output Port Paths ; 10 ; 10 ;+---------------------------------+-------+------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Status Summary ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+; Target ; Clock ; Type ; Status ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; Constrained ;; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; Constrained ;; din_a ; din_a ; Base ; Constrained ;; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; Base ; Constrained ;; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; Constrained ;; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; Constrained ;+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------++---------------------------------------------------------------------------------------------------+; Unconstrained Input Ports ;+------------+--------------------------------------------------------------------------------------+; Input Port ; Comment ;+------------+--------------------------------------------------------------------------------------+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;+------------+--------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------+; Unconstrained Output Ports ;+-------------+---------------------------------------------------------------------------------------+; Output Port ; Comment ;+-------------+---------------------------------------------------------------------------------------+; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;+-------------+---------------------------------------------------------------------------------------++---------------------------------------------------------------------------------------------------+; Unconstrained Input Ports ;+------------+--------------------------------------------------------------------------------------+; Input Port ; Comment ;+------------+--------------------------------------------------------------------------------------+; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;; sin_a ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;+------------+--------------------------------------------------------------------------------------++-----------------------------------------------------------------------------------------------------+; Unconstrained Output Ports ;+-------------+---------------------------------------------------------------------------------------+; Output Port ; Comment ;+-------------+---------------------------------------------------------------------------------------+; LED[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; LED[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; dout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;; sout_a(n) ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;+-------------+---------------------------------------------------------------------------------------++------------------------------------+; TimeQuest Timing Analyzer Messages ;+------------------------------------+Info: *******************************************************************Info: Running Quartus Prime TimeQuest Timing AnalyzerInfo: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite EditionInfo: Processing started: Mon Feb 5 00:57:45 2018Info: Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulightInfo: qsta_default_script.tcl version: #3Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo (21077): Low junction temperature is 0 degrees CInfo (21077): High junction temperature is 85 degrees CInfo (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: comboutInfo (332098): Cell: m_x|comb from: dataa to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandInfo: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ONInfo: Analyzing Slow 1100mV 85C ModelCritical Warning (332148): Timing requirements not metInfo (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.Info (332146): Worst-case setup slack is -4.369Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): -2.473 -27.460 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): -2.037 -45.867 din_aInfo (332119): -1.110 -2.017 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.322Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.322 0.000 FPGA_CLK1_50Info (332119): 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.393 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.547 0.000 din_aInfo (332119): 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case recovery slack is -0.289Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 14.466 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.563Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.563 0.000 FPGA_CLK1_50Info (332119): 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case minimum pulse width slack is 0.533Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.575 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.994 0.000 din_aInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 9.195 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 49 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 49Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 12.091 nsInfo (332114):Info: Analyzing Slow 1100mV 0C ModelInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: comboutInfo (332098): Cell: m_x|comb from: dataa to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandCritical Warning (332148): Timing requirements not metInfo (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.Info (332146): Worst-case setup slack is -4.207Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): -2.359 -27.122 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): -1.919 -41.436 din_aInfo (332119): -0.765 -1.140 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.211Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.211 0.000 FPGA_CLK1_50Info (332119): 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.388 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.530 0.000 din_aInfo (332119): 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case recovery slack is -0.346Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 14.772 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.464Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.464 0.000 FPGA_CLK1_50Info (332119): 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case minimum pulse width slack is 0.499Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.499 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.986 0.000 din_aInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 9.277 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 49 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 49Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 12.233 nsInfo (332114):Info: Analyzing Fast 1100mV 85C ModelInfo (334003): Started post-fitting delay annotationInfo (334004): Delay annotation completed successfullyInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: comboutInfo (332098): Cell: m_x|comb from: dataa to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandCritical Warning (332148): Timing requirements not metInfo (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.Info (332146): Worst-case setup slack is -2.086Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): -1.068 -12.429 din_aInfo (332119): -0.558 -5.149 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): -0.405 -0.405 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.122Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.175 0.000 FPGA_CLK1_50Info (332119): 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.217 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.242 0.000 din_aInfo (332119): 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case recovery slack is 0.648Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 16.136 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.424Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.424 0.000 FPGA_CLK1_50Info (332119): 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case minimum pulse width slack is 0.732Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.833 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 1.215 0.000 din_aInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 9.073 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 49 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 49Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 14.729 nsInfo (332114):Info: Analyzing Fast 1100mV 0C ModelInfo (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: comboutInfo (332098): Cell: m_x|comb from: dataa to: comboutInfo (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclkInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkoutInfo (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclkInfo (332152): The following assignments are ignored by the derive_clock_uncertainty commandCritical Warning (332148): Timing requirements not metInfo (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.Info (332146): Worst-case setup slack is -1.794Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): -0.704 -5.641 din_aInfo (332119): -0.395 -3.443 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): -0.113 -0.113 FPGA_CLK1_50Info (332146): Worst-case hold slack is 0.104Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.166 0.000 FPGA_CLK1_50Info (332119): 0.199 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 0.208 0.000 din_aInfo (332119): 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case recovery slack is 0.654Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 16.628 0.000 FPGA_CLK1_50Info (332146): Worst-case removal slack is 0.327Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.327 0.000 FPGA_CLK1_50Info (332119): 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332146): Worst-case minimum pulse width slack is 0.757Info (332119): Slack End Point TNS ClockInfo (332119): ========= =================== =====================Info (332119): 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_iInfo (332119): 0.823 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclkInfo (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]Info (332119): 1.293 0.000 din_aInfo (332119): 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_eInfo (332119): 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_iInfo (332119): 9.039 0.000 FPGA_CLK1_50Info (332114): Report Metastability: Found 49 synchronizer chains.Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.Info (332114): Number of Synchronizer Chains Found: 49Info (332114): Shortest Synchronizer Chain: 2 RegistersInfo (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000Info (332114): Worst Case Available Settling Time: 15.223 nsInfo (332114):Info (332102): Design is not fully constrained for setup requirementsInfo (332102): Design is not fully constrained for hold requirementsInfo: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warningsInfo: Peak virtual memory: 1444 megabytesInfo: Processing ended: Mon Feb 5 00:59:04 2018Info: Elapsed time: 00:01:19Info: Total CPU time (on all processors): 00:01:24