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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.sta.summary] - Rev 40

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TimeQuest Timing Analyzer Summary
------------------------------------------------------------

Type  : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -4.369
TNS   : -113.702

Type  : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -3.697
TNS   : -1112.931

Type  : Slow 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -3.138
TNS   : -13.527

Type  : Slow 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -2.473
TNS   : -27.460

Type  : Slow 1100mV 85C Model Setup 'din_a'
Slack : -2.037
TNS   : -45.867

Type  : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50'
Slack : -1.110
TNS   : -2.017

Type  : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50'
Slack : 0.322
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.336
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.393
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.470
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'din_a'
Slack : 0.547
TNS   : 0.000

Type  : Slow 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.624
TNS   : 0.000

Type  : Slow 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -0.289
TNS   : -4.795

Type  : Slow 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 5.248
TNS   : 0.000

Type  : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50'
Slack : 14.466
TNS   : 0.000

Type  : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50'
Slack : 0.563
TNS   : 0.000

Type  : Slow 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 1.308
TNS   : 0.000

Type  : Slow 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.746
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.533
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.575
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'din_a'
Slack : 0.994
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.301
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 3.952
TNS   : 0.000

Type  : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.195
TNS   : 0.000

Type  : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -4.207
TNS   : -109.829

Type  : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -3.461
TNS   : -1038.103

Type  : Slow 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -2.976
TNS   : -12.650

Type  : Slow 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -2.359
TNS   : -27.122

Type  : Slow 1100mV 0C Model Setup 'din_a'
Slack : -1.919
TNS   : -41.436

Type  : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50'
Slack : -0.765
TNS   : -1.140

Type  : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50'
Slack : 0.211
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.325
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.388
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.478
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'din_a'
Slack : 0.530
TNS   : 0.000

Type  : Slow 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.599
TNS   : 0.000

Type  : Slow 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -0.346
TNS   : -5.707

Type  : Slow 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 5.377
TNS   : 0.000

Type  : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50'
Slack : 14.772
TNS   : 0.000

Type  : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50'
Slack : 0.464
TNS   : 0.000

Type  : Slow 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 1.288
TNS   : 0.000

Type  : Slow 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.777
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.499
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.523
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'din_a'
Slack : 0.986
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.324
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 3.980
TNS   : 0.000

Type  : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.277
TNS   : 0.000

Type  : Fast 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -2.086
TNS   : -3.029

Type  : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -1.935
TNS   : -13.800

Type  : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -1.826
TNS   : -329.386

Type  : Fast 1100mV 85C Model Setup 'din_a'
Slack : -1.068
TNS   : -12.429

Type  : Fast 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -0.558
TNS   : -5.149

Type  : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50'
Slack : -0.405
TNS   : -0.405

Type  : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.122
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50'
Slack : 0.175
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.179
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.217
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'din_a'
Slack : 0.242
TNS   : 0.000

Type  : Fast 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.302
TNS   : 0.000

Type  : Fast 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.648
TNS   : 0.000

Type  : Fast 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 6.842
TNS   : 0.000

Type  : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50'
Slack : 16.136
TNS   : 0.000

Type  : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50'
Slack : 0.424
TNS   : 0.000

Type  : Fast 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.665
TNS   : 0.000

Type  : Fast 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.750
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.732
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.833
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'din_a'
Slack : 1.215
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.480
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 4.240
TNS   : 0.000

Type  : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.073
TNS   : 0.000

Type  : Fast 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : -1.794
TNS   : -2.071

Type  : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : -1.717
TNS   : -6.939

Type  : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : -1.507
TNS   : -230.983

Type  : Fast 1100mV 0C Model Setup 'din_a'
Slack : -0.704
TNS   : -5.641

Type  : Fast 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : -0.395
TNS   : -3.443

Type  : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50'
Slack : -0.113
TNS   : -0.113

Type  : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.104
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.164
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50'
Slack : 0.166
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.199
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'din_a'
Slack : 0.208
TNS   : 0.000

Type  : Fast 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.263
TNS   : 0.000

Type  : Fast 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.654
TNS   : 0.000

Type  : Fast 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 7.148
TNS   : 0.000

Type  : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50'
Slack : 16.628
TNS   : 0.000

Type  : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50'
Slack : 0.327
TNS   : 0.000

Type  : Fast 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 0.616
TNS   : 0.000

Type  : Fast 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 0.684
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i'
Slack : 0.757
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk'
Slack : 0.823
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]'
Slack : 1.250
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'din_a'
Slack : 1.293
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e'
Slack : 1.525
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i'
Slack : 4.335
TNS   : 0.000

Type  : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50'
Slack : 9.039
TNS   : 0.000

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