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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [simulation/] [modelsim/] [spw_fifo_ulight.vo] - Rev 32
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// Copyright (C) 2017 Intel Corporation. All rights reserved.// Your use of Intel Corporation's design tools, logic functions// and other software and tools, and its AMPP partner logic// functions, and any output files from any of the foregoing// (including device programming or simulation files), and any// associated documentation or information are expressly subject// to the terms and conditions of the Intel Program License// Subscription Agreement, the Intel Quartus Prime License Agreement,// the Intel MegaCore Function License Agreement, or other// applicable license agreement, including, without limitation,// that your use is for the sole purpose of programming logic// devices manufactured by Intel and sold by Intel or its// authorized distributors. Please refer to the applicable// agreement for further details.// VENDOR "Altera"// PROGRAM "Quartus Prime"// VERSION "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition"// DATE "08/24/2017 22:42:12"//// Device: Altera 5CSEMA4U23C6 Package UFBGA672////// This Verilog file should be used for ModelSim-Altera (Verilog) only//`timescale 1 ps/ 1 psmodule SPW_ULIGHT_FIFO (\dout_a(n) ,\sout_a(n) ,\din_a(n) ,\sin_a(n) ,FPGA_CLK1_50,KEY,din_a,sin_a,dout_a,sout_a,LED);output \dout_a(n) ;output \sout_a(n) ;input \din_a(n) ;input \sin_a(n) ;input FPGA_CLK1_50;input [1:0] KEY;input din_a;input sin_a;output dout_a;output sout_a;output [7:0] LED;// Design Ports Information// LED[5] => Location: PIN_AE26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[7] => Location: PIN_AA23, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// dout_a => Location: PIN_AG28, I/O Standard: LVDS, Current Strength: Default// sout_a => Location: PIN_AF20, I/O Standard: LVDS, Current Strength: Default// LED[0] => Location: PIN_W15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[1] => Location: PIN_AA24, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[2] => Location: PIN_V16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[3] => Location: PIN_V15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[4] => Location: PIN_AF26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// KEY[0] => Location: PIN_AH17, I/O Standard: 3.3-V LVTTL, Current Strength: Default// LED[6] => Location: PIN_Y16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// FPGA_CLK1_50 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: Default// KEY[1] => Location: PIN_AH16, I/O Standard: 3.3-V LVTTL, Current Strength: Default// din_a => Location: PIN_Y15, I/O Standard: LVDS, Current Strength: Default// sin_a => Location: PIN_AE20, I/O Standard: LVDS, Current Strength: Default// dout_a(n) => Location: PIN_AH27, I/O Standard: LVDS, Current Strength: Default// sout_a(n) => Location: PIN_AG20, I/O Standard: LVDS, Current Strength: Default// din_a(n) => Location: PIN_AA15, I/O Standard: LVDS, Current Strength: Default// sin_a(n) => Location: PIN_AD20, I/O Standard: LVDS, Current Strength: Defaultwire gnd;wire vcc;wire unknown;assign gnd = 1'b0;assign vcc = 1'b1;assign unknown = 1'bx;tri1 devclrn;tri1 devpor;tri1 devoe;wire \u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ;wire \u0|hps_0|fpga_interfaces|tpiu~trace_data ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 ;wire \u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ;wire \u0|hps_0|fpga_interfaces|fpga2hps~arready ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 ;wire \u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ;wire \KEY[0]~input_o ;wire \FPGA_CLK1_50~input_o ;wire \FPGA_CLK1_50~inputCLKENA0_outclk ;wire \KEY[1]~input_o ;wire \db_system_spwulight_b|PB_down~0_combout ;wire \db_system_spwulight_b|Add0~61_sumout ;wire \db_system_spwulight_b|counter~16_combout ;wire \db_system_spwulight_b|LessThan0~0_combout ;wire \db_system_spwulight_b|LessThan0~1_combout ;wire \db_system_spwulight_b|counter[0]~1_combout ;wire \db_system_spwulight_b|Add0~62 ;wire \db_system_spwulight_b|Add0~57_sumout ;wire \db_system_spwulight_b|counter~15_combout ;wire \db_system_spwulight_b|Add0~58 ;wire \db_system_spwulight_b|Add0~53_sumout ;wire \db_system_spwulight_b|counter~14_combout ;wire \db_system_spwulight_b|Add0~54 ;wire \db_system_spwulight_b|Add0~49_sumout ;wire \db_system_spwulight_b|counter~13_combout ;wire \db_system_spwulight_b|Add0~50 ;wire \db_system_spwulight_b|Add0~37_sumout ;wire \db_system_spwulight_b|counter~10_combout ;wire \db_system_spwulight_b|Add0~38 ;wire \db_system_spwulight_b|Add0~41_sumout ;wire \db_system_spwulight_b|counter~11_combout ;wire \db_system_spwulight_b|Add0~42 ;wire \db_system_spwulight_b|Add0~45_sumout ;wire \db_system_spwulight_b|counter~12_combout ;wire \db_system_spwulight_b|Add0~46 ;wire \db_system_spwulight_b|Add0~29_sumout ;wire \db_system_spwulight_b|counter~8_combout ;wire \db_system_spwulight_b|Add0~30 ;wire \db_system_spwulight_b|Add0~33_sumout ;wire \db_system_spwulight_b|counter~9_combout ;wire \db_system_spwulight_b|Add0~34 ;wire \db_system_spwulight_b|Add0~9_sumout ;wire \db_system_spwulight_b|counter~3_combout ;wire \db_system_spwulight_b|Add0~10 ;wire \db_system_spwulight_b|Add0~13_sumout ;wire \db_system_spwulight_b|counter~4_combout ;wire \db_system_spwulight_b|Add0~14 ;wire \db_system_spwulight_b|Add0~17_sumout ;wire \db_system_spwulight_b|counter~5_combout ;wire \db_system_spwulight_b|Add0~18 ;wire \db_system_spwulight_b|Add0~21_sumout ;wire \db_system_spwulight_b|counter~6_combout ;wire \db_system_spwulight_b|Add0~22 ;wire \db_system_spwulight_b|Add0~25_sumout ;wire \db_system_spwulight_b|counter~7_combout ;wire \db_system_spwulight_b|Add0~26 ;wire \db_system_spwulight_b|Add0~1_sumout ;wire \db_system_spwulight_b|counter~0_combout ;wire \db_system_spwulight_b|Add0~2 ;wire \db_system_spwulight_b|Add0~5_sumout ;wire \db_system_spwulight_b|counter~2_combout ;wire \db_system_spwulight_b|aux_pb~0_combout ;wire \db_system_spwulight_b|PB_down~q ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ;wire \db_system_spwulight_b|aux_pb~1_combout ;wire \db_system_spwulight_b|aux_pb~q ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|router_001|Equal7~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal10~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~3_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal12~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|router_001|Equal1~4_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ;wire \A_SPW_TOP|tx_data|mem~0feeder_combout ;wire \sin_a~input_o ;wire \din_a~input_o ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~q ;wire \A_SPW_TOP|SPW|FSM|Add2~1_sumout ;wire \A_SPW_TOP|SPW|FSM|Add2~22 ;wire \A_SPW_TOP|SPW|FSM|Add2~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~18 ;wire \A_SPW_TOP|SPW|FSM|Add2~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~14 ;wire \A_SPW_TOP|SPW|FSM|Add2~10 ;wire \A_SPW_TOP|SPW|FSM|Add2~6 ;wire \A_SPW_TOP|SPW|FSM|Add2~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~46 ;wire \A_SPW_TOP|SPW|FSM|Add2~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~10_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~42 ;wire \A_SPW_TOP|SPW|FSM|Add2~37_sumout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|FSM|after850ns~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~38 ;wire \A_SPW_TOP|SPW|FSM|Add2~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~34 ;wire \A_SPW_TOP|SPW|FSM|Add2~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~7_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~1_combout ;wire \A_SPW_TOP|SPW|FSM|after850ns~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~2 ;wire \A_SPW_TOP|SPW|FSM|Add2~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~26 ;wire \A_SPW_TOP|SPW|FSM|Add2~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~5_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~2_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~0_combout ;wire \A_SPW_TOP|SPW|RX|always3~0_combout ;wire \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~2 ;wire \A_SPW_TOP|SPW|FSM|Add1~25_sumout ;wire \A_SPW_TOP|SPW|FSM|Equal2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~26 ;wire \A_SPW_TOP|SPW|FSM|Add1~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~22 ;wire \A_SPW_TOP|SPW|FSM|Add1~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~18 ;wire \A_SPW_TOP|SPW|FSM|Add1~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~14 ;wire \A_SPW_TOP|SPW|FSM|Add1~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~10 ;wire \A_SPW_TOP|SPW|FSM|Add1~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~6 ;wire \A_SPW_TOP|SPW|FSM|Add1~46 ;wire \A_SPW_TOP|SPW|FSM|Add1~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~42 ;wire \A_SPW_TOP|SPW|FSM|Add1~30 ;wire \A_SPW_TOP|SPW|FSM|Add1~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~10_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~38 ;wire \A_SPW_TOP|SPW|FSM|Add1~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ;wire \m_x|counter_neg[0]~feeder_combout ;wire \m_x|Selector4~0_combout ;wire \m_x|Selector1~0_combout ;wire \m_x|Selector2~0_combout ;wire \m_x|Selector2~1_combout ;wire \m_x|WideOr7~0_combout ;wire \m_x|Selector5~0_combout ;wire \m_x|Selector0~0_combout ;wire \m_x|Equal1~0_combout ;wire \m_x|control_bit_found~q ;wire \m_x|Selector0~1_combout ;wire \m_x|Selector0~2_combout ;wire \m_x|is_control~q ;wire \m_x|Selector3~0_combout ;wire \m_x|always2~1_combout ;wire \m_x|Selector5~1_combout ;wire \m_x|Selector5~2_combout ;wire \m_x|Selector5~3_combout ;wire \m_x|always2~0_combout ;wire \m_x|always1~0_combout ;wire \m_x|bit_c_0~q ;wire \m_x|bit_c_2~feeder_combout ;wire \m_x|bit_c_2~q ;wire \m_x|control_r[2]~feeder_combout ;wire \m_x|control_p_r[2]~feeder_combout ;wire \m_x|ready_control_p_r~0_combout ;wire \m_x|ready_control_p_r~q ;wire \m_x|info[12]~feeder_combout ;wire \m_x|Equal1~1_combout ;wire \m_x|ready_data_p~combout ;wire \m_x|ready_data_p_r~0_combout ;wire \m_x|ready_data_p_r~1_combout ;wire \m_x|ready_data_p_r~q ;wire \m_x|data_l_r[7]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ;wire \m_x|bit_c_1~q ;wire \m_x|bit_c_3~q ;wire \m_x|control_r[3]~feeder_combout ;wire \m_x|control_p_r[3]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|router_001|Equal13~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal13~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|router_001|Equal5~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|router_001|Equal18~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal18~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal19~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|router|Equal13~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ;wire \u0|mm_interconnect_0|router|Equal15~0_combout ;wire \u0|mm_interconnect_0|router|Equal15~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~2_combout ;wire \u0|mm_interconnect_0|router|Equal7~2_combout ;wire \u0|mm_interconnect_0|router|Equal7~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~3_combout ;wire \u0|mm_interconnect_0|router|Equal7~4_combout ;wire \u0|mm_interconnect_0|router|Equal6~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~1_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~0_combout ;wire \u0|mm_interconnect_0|router|Equal14~1_combout ;wire \u0|mm_interconnect_0|router|Equal21~0_combout ;wire \u0|mm_interconnect_0|router|Equal20~0_combout ;wire \u0|mm_interconnect_0|router|src_data[102]~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~2_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~3_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~1_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~7_combout ;wire \u0|mm_interconnect_0|router|src_data[104]~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ;wire \u0|mm_interconnect_0|router|src_data[101]~8_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|saved_grant[0]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ;wire \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|router_001|Equal17~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal17~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ;wire \u0|mm_interconnect_0|router|Equal17~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~4_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal7~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal7~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~9_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~201_combout ;wire \u0|mm_interconnect_0|router_001|Equal8~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~198_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~199_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~202_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~196_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~197_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~200_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ;wire \u0|mm_interconnect_0|router_001|Equal3~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal3~1_combout ;wire \u0|mm_interconnect_0|router_001|src_data[103]~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~203_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router_001|Equal11~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~58_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|router_001|Equal9~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~204_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~205_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~194_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~193_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~195_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~188_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~189_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~190_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~186_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~187_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~192_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~191_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~182_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~180_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~176_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~177_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~178_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~179_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~183_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~184_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~185_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~181_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~172_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~171_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~173_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~174_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~175_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~170_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~168_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~169_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~166_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~167_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ;wire \u0|mm_interconnect_0|router|Equal13~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~156_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~157_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~158_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~159_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~160_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~162_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~161_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~163_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~164_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~165_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~153_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~154_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~155_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~148_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~149_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~146_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~147_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~150_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~151_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~152_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~141_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~136_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~137_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~142_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~140_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~138_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~139_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~144_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~143_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~145_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~126_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~127_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~128_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~129_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~132_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~131_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~133_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~134_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~135_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~130_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~116_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~117_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~124_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~123_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~125_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~118_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~119_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~120_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~122_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~121_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~108_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~109_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~110_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~112_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~106_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~107_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~111_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~114_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~113_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~115_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~98_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~99_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~101_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~96_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~97_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~102_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~103_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~104_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~105_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~100_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~88_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~89_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~92_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~93_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~94_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~95_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~90_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~86_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~87_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~91_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ;wire \u0|link_start|data_out~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ;wire \u0|link_start|always0~0_combout ;wire \u0|link_start|data_out~q ;wire \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|auto_start|always0~0_combout ;wire \u0|auto_start|data_out~q ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector3~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector3~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector1~0_combout ;wire \A_SPW_TOP|SPW|RX|control_bit_found~q ;wire \A_SPW_TOP|SPW|RX|Selector0~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~2_combout ;wire \A_SPW_TOP|SPW|RX|is_control~q ;wire \A_SPW_TOP|SPW|RX|always2~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p~combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~q ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~q ;wire \A_SPW_TOP|SPW|RX|last_is_control~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_control~feeder_combout ;wire \A_SPW_TOP|SPW|RX|last_is_control~q ;wire \A_SPW_TOP|SPW|RX|bit_c_0~q ;wire \A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_1~q ;wire \A_SPW_TOP|SPW|RX|control_r[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_2~q ;wire \A_SPW_TOP|SPW|RX|control_r[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always8~0_combout ;wire \A_SPW_TOP|SPW|RX|always11~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ;wire \A_SPW_TOP|SPW|RX|last_is_data~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_data~1_combout ;wire \A_SPW_TOP|SPW|RX|last_is_data~q ;wire \A_SPW_TOP|SPW|RX|last_is_timec~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_timec~q ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~q ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~q ;wire \A_SPW_TOP|SPW|FSM|always0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~q ;wire \A_SPW_TOP|SPW|FSM|Selector4~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~1_combout ;wire \A_SPW_TOP|SPW|FSM|always2~0_combout ;wire \A_SPW_TOP|SPW|FSM|always0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~6_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|link_disable|always0~0_combout ;wire \u0|link_disable|data_out~q ;wire \A_SPW_TOP|SPW|FSM|Selector4~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~4_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~5_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ;wire \A_SPW_TOP|SPW|FSM|Selector2~5_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~4_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ;wire \A_SPW_TOP|SPW|FSM|Selector3~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector3~1_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.started~q ;wire \A_SPW_TOP|SPW|FSM|Selector1~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector1~1_combout ;wire \A_SPW_TOP|SPW|FSM|after128us~13_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~30 ;wire \A_SPW_TOP|SPW|FSM|Add0~26 ;wire \A_SPW_TOP|SPW|FSM|Add0~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~22 ;wire \A_SPW_TOP|SPW|FSM|Add0~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~18 ;wire \A_SPW_TOP|SPW|FSM|Add0~14 ;wire \A_SPW_TOP|SPW|FSM|Add0~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~10 ;wire \A_SPW_TOP|SPW|FSM|Add0~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~6 ;wire \A_SPW_TOP|SPW|FSM|Add0~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~2 ;wire \A_SPW_TOP|SPW|FSM|Add0~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~12_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~46 ;wire \A_SPW_TOP|SPW|FSM|Add0~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~42 ;wire \A_SPW_TOP|SPW|FSM|Add0~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~10_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~2_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector1~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ;wire \A_SPW_TOP|SPW|FSM|always2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~0_combout ;wire \A_SPW_TOP|SPW|FSM|after128us[3]~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~38 ;wire \A_SPW_TOP|SPW|FSM|Add0~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~2_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ;wire \A_SPW_TOP|SPW|FSM|after64us[8]~0_combout ;wire \A_SPW_TOP|SPW|FSM|after64us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~12_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~1_combout ;wire \A_SPW_TOP|SPW|FSM|rx_resetn~0_combout ;wire \A_SPW_TOP|SPW|FSM|rx_resetn~q ;wire \A_SPW_TOP|SPW|RX|WideOr7~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~2_combout ;wire \A_SPW_TOP|SPW|RX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|RX|always2~1_combout ;wire \A_SPW_TOP|SPW|RX|always1~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data~combout ;wire \A_SPW_TOP|SPW|RX|bit_d_0~q ;wire \A_SPW_TOP|SPW|RX|bit_d_2~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_2~q ;wire \A_SPW_TOP|SPW|RX|timecode[7]~0_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_4~q ;wire \A_SPW_TOP|SPW|RX|bit_d_1~q ;wire \A_SPW_TOP|SPW|RX|bit_d_3~q ;wire \A_SPW_TOP|SPW|RX|timecode[4]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|timecode[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_5~q ;wire \A_SPW_TOP|SPW|RX|always9~0_combout ;wire \A_SPW_TOP|SPW|RX|last_was_control~q ;wire \A_SPW_TOP|SPW|RX|last_was_timec~q ;wire \A_SPW_TOP|SPW|RX|rx_error~1_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_7~q ;wire \A_SPW_TOP|SPW|RX|bit_d_6~q ;wire \A_SPW_TOP|SPW|RX|bit_c_3~q ;wire \A_SPW_TOP|SPW|RX|control_r[3]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~6_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~4_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data[9]~0_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~4_combout ;wire \A_SPW_TOP|SPW|RX|last_was_data~q ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~5_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~7_combout ;wire \A_SPW_TOP|SPW|RX|always9~6_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~8_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_8~q ;wire \A_SPW_TOP|SPW|RX|data[8]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_9~q ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[9]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data[9]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~3_combout ;wire \A_SPW_TOP|SPW|RX|data_l_r[4]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~2_combout ;wire \A_SPW_TOP|SPW|RX|always9~3_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~5_combout ;wire \A_SPW_TOP|SPW|RX|always9~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~9_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~q ;wire \A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout ;wire \A_SPW_TOP|rx_data|credit_counter[0]~8_combout ;wire \A_SPW_TOP|rx_data|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|data_read_en_rx|always0~0_combout ;wire \u0|data_read_en_rx|data_out~q ;wire \A_SPW_TOP|SPW|RX|rx_data_take~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_take~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_take~q ;wire \A_SPW_TOP|SPW|RX|rx_data_take_0~q ;wire \A_SPW_TOP|SPW|RX|rx_buffer_write~q ;wire \A_SPW_TOP|rx_data|Add0~2 ;wire \A_SPW_TOP|rx_data|Add0~5_sumout ;wire \A_SPW_TOP|rx_data|Add0~6 ;wire \A_SPW_TOP|rx_data|Add0~9_sumout ;wire \A_SPW_TOP|rx_data|counter[2]~feeder_combout ;wire \A_SPW_TOP|rx_data|Add0~10 ;wire \A_SPW_TOP|rx_data|Add0~13_sumout ;wire \A_SPW_TOP|rx_data|counter[3]~feeder_combout ;wire \A_SPW_TOP|rx_data|Add0~14 ;wire \A_SPW_TOP|rx_data|Add0~17_sumout ;wire \A_SPW_TOP|rx_data|counter[4]~feeder_combout ;wire \A_SPW_TOP|rx_data|Add0~18 ;wire \A_SPW_TOP|rx_data|Add0~21_sumout ;wire \A_SPW_TOP|rx_data|counter[5]~feeder_combout ;wire \A_SPW_TOP|rx_data|Equal1~0_combout ;wire \A_SPW_TOP|rx_data|f_empty~q ;wire \A_SPW_TOP|rx_data|block_read~0_combout ;wire \A_SPW_TOP|rx_data|block_read~q ;wire \A_SPW_TOP|rx_data|counter~0_combout ;wire \A_SPW_TOP|rx_data|Equal0~0_combout ;wire \A_SPW_TOP|rx_data|f_full~q ;wire \A_SPW_TOP|rx_data|block_write~0_combout ;wire \A_SPW_TOP|rx_data|block_write~q ;wire \A_SPW_TOP|rx_data|mem~12_combout ;wire \A_SPW_TOP|rx_data|Add1~2_combout ;wire \A_SPW_TOP|rx_data|Add1~1_combout ;wire \A_SPW_TOP|rx_data|Add1~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter~3_combout ;wire \A_SPW_TOP|rx_data|credit_counter[3]~4_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~1_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~2_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~3_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~4_combout ;wire \A_SPW_TOP|rx_data|always2~1_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~5_combout ;wire \A_SPW_TOP|rx_data|rd_ptr~0_combout ;wire \A_SPW_TOP|rx_data|always2~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter[3]~1_combout ;wire \A_SPW_TOP|rx_data|credit_counter~2_combout ;wire \A_SPW_TOP|rx_data|credit_counter~5_combout ;wire \A_SPW_TOP|rx_data|credit_counter~0_combout ;wire \A_SPW_TOP|rx_data|always0~0_combout ;wire \A_SPW_TOP|rx_data|overflow_credit_error~q ;wire \A_SPW_TOP|SPW|FSM|Selector5~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector5~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.run~q ;wire \A_SPW_TOP|tx_reset_n~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|write_en_tx|always0~0_combout ;wire \u0|write_en_tx|data_out~q ;wire \A_SPW_TOP|tx_data|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|timecode_tx_enable|always0~0_combout ;wire \u0|timecode_tx_enable|data_out~q ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~q ;wire \A_SPW_TOP|rx_data|open_slot_fct~q ;wire \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ;wire \A_SPW_TOP|tx_data|write_tx~0_combout ;wire \A_SPW_TOP|tx_data|write_tx~q ;wire \A_SPW_TOP|SPW|TX|always7~3_combout ;wire \A_SPW_TOP|SPW|TX|always7~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|TX|Add2~0_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~3_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~q ;wire \A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ;wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout ;wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~q ;wire \A_SPW_TOP|SPW|TX|fct_flag~4_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag[0]~10_combout ;wire \A_SPW_TOP|SPW|TX|always7~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector3~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ;wire \A_SPW_TOP|SPW|TX|enable_time_code~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~3_combout ;wire \A_SPW_TOP|SPW|TX|Add4~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~2_combout ;wire \A_SPW_TOP|SPW|TX|last_type~21_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~0_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~q ;wire \A_SPW_TOP|tx_data|counter~0_combout ;wire \A_SPW_TOP|tx_data|Add0~2 ;wire \A_SPW_TOP|tx_data|Add0~5_sumout ;wire \A_SPW_TOP|tx_data|Add0~6 ;wire \A_SPW_TOP|tx_data|Add0~10 ;wire \A_SPW_TOP|tx_data|Add0~13_sumout ;wire \A_SPW_TOP|tx_data|Add0~14 ;wire \A_SPW_TOP|tx_data|Add0~17_sumout ;wire \A_SPW_TOP|tx_data|Add0~18 ;wire \A_SPW_TOP|tx_data|Add0~21_sumout ;wire \A_SPW_TOP|tx_data|Equal0~0_combout ;wire \A_SPW_TOP|tx_data|f_full~q ;wire \A_SPW_TOP|tx_data|block_write~0_combout ;wire \A_SPW_TOP|tx_data|block_write~q ;wire \A_SPW_TOP|tx_data|Add0~9_sumout ;wire \A_SPW_TOP|tx_data|Equal1~0_combout ;wire \A_SPW_TOP|tx_data|f_empty~q ;wire \A_SPW_TOP|tx_data|block_read~0_combout ;wire \A_SPW_TOP|tx_data|block_read~q ;wire \A_SPW_TOP|tx_data|mem~0_q ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ;wire \u0|write_data_fifo_tx|data_out[8]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|write_data_fifo_tx|always0~0_combout ;wire \A_SPW_TOP|tx_data|wr_ptr[0]~0_combout ;wire \A_SPW_TOP|tx_data|mem~14_combout ;wire \A_SPW_TOP|tx_data|comb~0_combout ;wire \A_SPW_TOP|tx_data|Add2~1_combout ;wire \A_SPW_TOP|tx_data|Add2~2_combout ;wire \A_SPW_TOP|tx_data|Add2~3_combout ;wire \A_SPW_TOP|tx_data|Add2~4_combout ;wire \A_SPW_TOP|tx_data|Add2~0_combout ;wire \A_SPW_TOP|tx_data|mem~12_combout ;wire \A_SPW_TOP|tx_data|mem~13_combout ;wire \A_SPW_TOP|tx_data|mem~9_q ;wire \A_SPW_TOP|tx_data|block_read~_wirecell_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ;wire \u0|write_data_fifo_tx|data_out[0]~feeder_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~1_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~2_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~3_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~4_combout ;wire \A_SPW_TOP|tx_data|Add3~0_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~5_combout ;wire \A_SPW_TOP|tx_data|rd_ptr~0_combout ;wire \~QUARTUS_CREATED_GND~I_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ;wire \u0|write_data_fifo_tx|data_out[3]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ;wire \u0|write_data_fifo_tx|data_out[4]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ;wire \u0|write_data_fifo_tx|data_out[5]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ;wire \u0|write_data_fifo_tx|data_out[7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 ;wire \A_SPW_TOP|tx_data|data_out~9_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem~10_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[21]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[9]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem~11_combout ;wire \A_SPW_TOP|tx_data|data_out~10_combout ;wire \A_SPW_TOP|tx_data|data_out~2_combout ;wire \A_SPW_TOP|SPW|TX|last_type~11_combout ;wire \A_SPW_TOP|SPW|TX|Equal5~4_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~1_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~8_combout ;wire \A_SPW_TOP|SPW|TX|Equal5~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_fct~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_fct~q ;wire \A_SPW_TOP|SPW|TX|always7~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~14_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~q ;wire \A_SPW_TOP|SPW|TX|always7~1_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~6_combout ;wire \A_SPW_TOP|SPW|RX|always8~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct~q ;wire \A_SPW_TOP|SPW|TX|always7~2_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~1_combout ;wire \A_SPW_TOP|SPW|TX|block_sum~0_combout ;wire \A_SPW_TOP|SPW|TX|block_sum~q ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~0_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~13_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~12_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~2_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[3]~4_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~14_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~8_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~6_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~2_combout ;wire \A_SPW_TOP|SPW|TX|Add4~1_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~4_combout ;wire \A_SPW_TOP|SPW|TX|first_time~feeder_combout ;wire \A_SPW_TOP|SPW|TX|first_time~q ;wire \A_SPW_TOP|SPW|TX|last_type~10_combout ;wire \A_SPW_TOP|SPW|TX|hold_null~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_null~q ;wire \A_SPW_TOP|SPW|FSM|WideOr0~combout ;wire \A_SPW_TOP|SPW|FSM|send_null_tx~q ;wire \A_SPW_TOP|SPW|TX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ;wire \A_SPW_TOP|SPW|TX|Selector1~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ;wire \A_SPW_TOP|SPW|TX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ;wire \A_SPW_TOP|SPW|TX|tx_sout~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ;wire \u0|timecode_tx_data|data_out[3]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|timecode_tx_data|always0~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ;wire \u0|timecode_tx_data|data_out[6]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ;wire \u0|timecode_tx_data|data_out[7]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ;wire \u0|timecode_tx_data|data_out[4]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ;wire \u0|timecode_tx_data|data_out[0]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ;wire \u0|timecode_tx_data|data_out[2]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ;wire \u0|timecode_tx_data|data_out[1]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ;wire \A_SPW_TOP|SPW|TX|last_type~15_combout ;wire \A_SPW_TOP|SPW|TX|last_type~16_combout ;wire \A_SPW_TOP|SPW|TX|last_type~17_combout ;wire \A_SPW_TOP|SPW|TX|last_type~12_combout ;wire \A_SPW_TOP|SPW|TX|last_type~13_combout ;wire \A_SPW_TOP|SPW|TX|last_type~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type.TIMEC~q ;wire \A_SPW_TOP|SPW|TX|Equal5~2_combout ;wire \A_SPW_TOP|SPW|TX|last_type~18_combout ;wire \A_SPW_TOP|SPW|TX|last_type~19_combout ;wire \A_SPW_TOP|SPW|TX|last_type.DATA~q ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 ;wire \A_SPW_TOP|tx_data|mem~7_q ;wire \A_SPW_TOP|tx_data|data_out~15_combout ;wire \A_SPW_TOP|tx_data|data_out~16_combout ;wire \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 ;wire \A_SPW_TOP|tx_data|mem~6_q ;wire \A_SPW_TOP|tx_data|data_out~5_combout ;wire \A_SPW_TOP|tx_data|data_out~6_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 ;wire \A_SPW_TOP|tx_data|mem~8_q ;wire \A_SPW_TOP|tx_data|data_out~0_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[20]~feeder_combout ;wire \A_SPW_TOP|tx_data|data_out~1_combout ;wire \A_SPW_TOP|tx_data|mem~5_q ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 ;wire \A_SPW_TOP|tx_data|data_out~7_combout ;wire \A_SPW_TOP|tx_data|data_out~8_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0_bypass[15]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 ;wire \A_SPW_TOP|tx_data|mem~3_q ;wire \A_SPW_TOP|tx_data|data_out~17_combout ;wire \A_SPW_TOP|tx_data|data_out~18_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 ;wire \A_SPW_TOP|tx_data|mem~4_q ;wire \A_SPW_TOP|tx_data|data_out~3_combout ;wire \A_SPW_TOP|tx_data|data_out~4_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 ;wire \A_SPW_TOP|tx_data|mem~2_q ;wire \A_SPW_TOP|tx_data|data_out~11_combout ;wire \A_SPW_TOP|tx_data|data_out~12_combout ;wire \A_SPW_TOP|tx_data|mem~1_q ;wire \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ;wire \A_SPW_TOP|tx_data|data_out~13_combout ;wire \A_SPW_TOP|tx_data|data_out~14_combout ;wire \A_SPW_TOP|SPW|TX|last_type~28_combout ;wire \A_SPW_TOP|SPW|TX|last_type~22_combout ;wire \A_SPW_TOP|SPW|TX|last_type.EOP~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_null~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_null~2_combout ;wire \A_SPW_TOP|SPW|TX|enable_n_char~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~26_combout ;wire \A_SPW_TOP|SPW|TX|last_type~27_combout ;wire \A_SPW_TOP|SPW|TX|last_type.FCT~q ;wire \A_SPW_TOP|SPW|TX|last_type~24_combout ;wire \A_SPW_TOP|SPW|TX|last_type~23_combout ;wire \A_SPW_TOP|SPW|TX|last_type~25_combout ;wire \A_SPW_TOP|SPW|TX|last_type.NULL~q ;wire \A_SPW_TOP|SPW|TX|tx_dout~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~6_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~8_combout ;wire \A_SPW_TOP|SPW|TX|Equal5~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~9_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~5_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ;wire \A_SPW_TOP|SPW|TX|always3~4_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[2]~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ;wire \A_SPW_TOP|SPW|TX|Equal5~1_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~22_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~27_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~12_combout ;wire \A_SPW_TOP|SPW|TX|always3~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~23_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~19_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ;wire \A_SPW_TOP|SPW|TX|always3~1_combout ;wire \A_SPW_TOP|SPW|TX|always3~5_combout ;wire \A_SPW_TOP|SPW|TX|always3~2_combout ;wire \A_SPW_TOP|SPW|TX|always3~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~4_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout~2_combout ;wire \A_SPW_TOP|SPW|TX|last_tx_sout~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~25_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~24_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~11_combout ;wire \A_SPW_TOP|SPW|TX|last_tx_dout~q ;wire \A_SPW_TOP|SPW|TX|tx_sout~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~10_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~q ;wire \m_x|always3~0_combout ;wire \m_x|control_r[1]~feeder_combout ;wire \m_x|control_p_r[1]~feeder_combout ;wire \m_x|info[11]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \m_x|control_r[0]~feeder_combout ;wire \m_x|info[10]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[9]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \A_SPW_TOP|rx_data|comb~0_combout ;wire \A_SPW_TOP|rx_data|block_read~_wirecell_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag[8]~9_combout ;wire \A_SPW_TOP|rx_data|wr_ptr[0]~0_combout ;wire \A_SPW_TOP|rx_data|Add4~1_combout ;wire \A_SPW_TOP|rx_data|Add4~2_combout ;wire \A_SPW_TOP|rx_data|Add4~3_combout ;wire \A_SPW_TOP|rx_data|Add4~4_combout ;wire \A_SPW_TOP|rx_data|Add4~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 ;wire \A_SPW_TOP|rx_data|mem~0feeder_combout ;wire \A_SPW_TOP|rx_data|mem~0_q ;wire \A_SPW_TOP|rx_data|mem~14_combout ;wire \A_SPW_TOP|rx_data|mem~13_combout ;wire \A_SPW_TOP|rx_data|mem~9_q ;wire \A_SPW_TOP|rx_data|data_out~16_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[11]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem~10_combout ;wire \A_SPW_TOP|rx_data|mem~11_combout ;wire \A_SPW_TOP|rx_data|data_out~17_combout ;wire \A_SPW_TOP|rx_data|always1~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ;wire \m_x|info[8]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~83_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~84_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~85_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~81_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[20]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 ;wire \A_SPW_TOP|rx_data|mem~8_q ;wire \A_SPW_TOP|rx_data|data_out~14_combout ;wire \A_SPW_TOP|rx_data|data_out~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~82_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~80_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~79_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~206_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ;wire \u0|mm_interconnect_0|router|Equal14~0_combout ;wire \u0|mm_interconnect_0|router|Equal16~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~75_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~76_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[19]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 ;wire \A_SPW_TOP|rx_data|mem~7_q ;wire \A_SPW_TOP|rx_data|data_out~12_combout ;wire \A_SPW_TOP|rx_data|data_out~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~77_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~78_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~210_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_rx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~68_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~67_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~66_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_tx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~72_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 ;wire \A_SPW_TOP|rx_data|mem~6_q ;wire \A_SPW_TOP|rx_data|data_out~10_combout ;wire \A_SPW_TOP|rx_data|data_out~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~70_combout ;wire \m_x|bit_d_1~q ;wire \m_x|bit_d_3~feeder_combout ;wire \m_x|bit_d_3~q ;wire \m_x|bit_d_5~feeder_combout ;wire \m_x|bit_d_5~q ;wire \m_x|dta_timec_p[2]~feeder_combout ;wire \m_x|data~9_combout ;wire \m_x|last_is_timec~0_combout ;wire \m_x|last_is_timec~q ;wire \m_x|last_is_control~0_combout ;wire \m_x|last_is_control~q ;wire \m_x|last_is_data~0_combout ;wire \m_x|last_is_data~q ;wire \m_x|data[8]~1_combout ;wire \m_x|data[8]~2_combout ;wire \m_x|dta_timec[6]~feeder_combout ;wire \m_x|dta_timec_p[6]~feeder_combout ;wire \m_x|data~5_combout ;wire \m_x|bit_d_0~q ;wire \m_x|bit_d_2~feeder_combout ;wire \m_x|bit_d_2~q ;wire \m_x|bit_d_4~q ;wire \m_x|dta_timec_p[3]~feeder_combout ;wire \m_x|data~8_combout ;wire \m_x|data~6_combout ;wire \m_x|dta_timec[4]~feeder_combout ;wire \m_x|dta_timec_p[4]~feeder_combout ;wire \m_x|data~7_combout ;wire \m_x|dta_timec[7]~feeder_combout ;wire \m_x|dta_timec_p[7]~feeder_combout ;wire \m_x|data~4_combout ;wire \m_x|always9~4_combout ;wire \m_x|bit_d_6~q ;wire \m_x|bit_d_8~feeder_combout ;wire \m_x|bit_d_8~q ;wire \m_x|dta_timec[8]~feeder_combout ;wire \m_x|dta_timec_p[8]~feeder_combout ;wire \m_x|data~0_combout ;wire \m_x|rx_error~6_combout ;wire \m_x|bit_d_7~q ;wire \m_x|data~3_combout ;wire \m_x|dta_timec[1]~feeder_combout ;wire \m_x|dta_timec_p[1]~feeder_combout ;wire \m_x|data~10_combout ;wire \m_x|always9~5_combout ;wire \m_x|last_was_data~q ;wire \m_x|last_was_timec~q ;wire \m_x|last_was_control~q ;wire \m_x|rx_error~8_combout ;wire \m_x|rx_error~7_combout ;wire \m_x|rx_error~9_combout ;wire \m_x|rx_error~2_combout ;wire \m_x|timecode[5]~feeder_combout ;wire \m_x|timecode[7]~0_combout ;wire \m_x|always9~0_combout ;wire \m_x|rx_error~0_combout ;wire \m_x|rx_error~3_combout ;wire \m_x|always9~3_combout ;wire \m_x|rx_error~4_combout ;wire \m_x|rx_error~5_combout ;wire \m_x|data_l_r[7]~1_combout ;wire \m_x|always9~2_combout ;wire \m_x|always9~1_combout ;wire \m_x|rx_error~1_combout ;wire \m_x|rx_error~10_combout ;wire \m_x|rx_error~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~71_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~69_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~73_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~74_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~58_combout ;wire \m_x|always0~0_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 ;wire \A_SPW_TOP|rx_data|mem~5_q ;wire \A_SPW_TOP|rx_data|data_out~8_combout ;wire \A_SPW_TOP|rx_data|data_out~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~61_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~60_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|led_pio_test|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~59_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~62_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fsm_info|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~63_combout ;wire \u0|counter_rx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ;wire \u0|counter_tx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~64_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~218_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~214_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~7_combout ;wire \u0|mm_interconnect_0|router|Equal7~8_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~5_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 ;wire \A_SPW_TOP|rx_data|mem~4_q ;wire \A_SPW_TOP|rx_data|data_out~6_combout ;wire \A_SPW_TOP|rx_data|data_out~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~53_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~51_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~52_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~54_combout ;wire \m_x|always10~0_combout ;wire \m_x|rx_got_null~1_combout ;wire \m_x|rx_got_null~0_combout ;wire \m_x|rx_got_null~q ;wire \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[3]~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|counter_tx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|counter_rx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ;wire \u0|fsm_info|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~226_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~50_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~222_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ;wire \u0|counter_tx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ;wire \u0|counter_rx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|fsm_info|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~234_combout ;wire \m_x|rx_got_nchar~0_combout ;wire \m_x|rx_got_nchar~1_combout ;wire \m_x|rx_got_nchar~q ;wire \m_x|info[2]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~40_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[15]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem~3_q ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 ;wire \A_SPW_TOP|rx_data|data_out~4_combout ;wire \A_SPW_TOP|rx_data|data_out~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~42_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~41_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|clock_sel|readdata[2]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~230_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal4~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[14]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem~2_q ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 ;wire \A_SPW_TOP|rx_data|data_out~2_combout ;wire \A_SPW_TOP|rx_data|data_out~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~30_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ;wire \m_x|rx_got_time_code~0_combout ;wire \m_x|rx_got_time_code~q ;wire \u0|data_info|readdata[1]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ;wire \u0|clock_sel|always0~0_combout ;wire \u0|clock_sel|readdata[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ;wire \u0|counter_tx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ;wire \u0|counter_rx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|fsm_info|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~242_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~238_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal21~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ;wire \u0|clock_sel|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|timecode_tx_enable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ;wire \u0|link_disable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ;wire \u0|write_en_tx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ;wire \u0|counter_tx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|auto_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ;wire \u0|counter_rx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ;wire \u0|fsm_info|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_full_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ;wire \u0|data_read_en_rx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre[0]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_full_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ;wire \A_SPW_TOP|rx_data|mem_rtl_0_bypass[13]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem~1_q ;wire \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout ;wire \A_SPW_TOP|rx_data|data_out~0_combout ;wire \A_SPW_TOP|rx_data|data_out~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ;wire \u0|link_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~1_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|timecode_tx_ready|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[2]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[1]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_burstwrap[3]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~q ;wire \u0|timecode_ready_rx|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ;wire \m_x|rx_got_fct~0_combout ;wire \m_x|rx_got_fct~q ;wire \m_x|info[0]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ;wire \u0|mm_interconnect_0|router_001|Equal16~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal16~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ;wire \u0|mm_interconnect_0|router_001|src_data[103]~0_combout ;wire \u0|mm_interconnect_0|router_001|src_data[101]~3_combout ;wire \u0|mm_interconnect_0|router_001|src_data[104]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|router_001|src_data[102]~2_combout ;wire \u0|mm_interconnect_0|router_001|src_data[100]~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ;wire \u0|mm_interconnect_0|router_001|Equal6~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~28_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~29_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~5_combout ;wire \u0|mm_interconnect_0|router|Equal7~6_combout ;wire \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ;wire \u0|mm_interconnect_0|router_001|Equal1~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal20~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal15~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ;wire \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~10 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[4]~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~q ;wire [9:0] \m_x|dta_timec_p ;wire [9:0] \m_x|dta_timec ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_r ;wire [5:0] \A_SPW_TOP|SPW|RX|counter_neg ;wire [2:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits ;wire [9:0] \m_x|data_l_r ;wire [9:0] \m_x|data ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [8:0] \A_SPW_TOP|SPW|RX|rx_data_flag ;wire [5:0] \A_SPW_TOP|rx_data|wr_ptr ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [9:0] \A_SPW_TOP|SPW|RX|data_l_r ;wire [9:0] \A_SPW_TOP|SPW|RX|data ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter ;wire [5:0] \A_SPW_TOP|rx_data|rd_ptr ;wire [3:0] \A_SPW_TOP|SPW|RX|control_l_r ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter_100 ;wire [5:0] \A_SPW_TOP|tx_data|wr_ptr ;wire [11:0] \A_SPW_TOP|SPW|FSM|after850ns ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [0:21] \A_SPW_TOP|rx_data|mem_rtl_0_bypass ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after64us ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [3:0] \m_x|control_r ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre ;wire [2:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count ;wire [152:0] \u0|mm_interconnect_0|rsp_mux_001|src_payload ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften ;wire [7:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_007|src_data ;wire [3:0] \m_x|control ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg ;wire [2:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used ;wire [7:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [7:0] \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [31:0] \u0|fifo_full_tx_status|readdata ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_011|src_payload ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [0:0] \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg ;wire [0:0] \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [3:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [0:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|saved_grant ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \m_x|control_p_r ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_009|src_payload ;wire [3:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used ;wire [15:0] \db_system_spwulight_b|counter ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|saved_grant ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter ;wire [7:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux|src_data ;wire [128:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [7:0] \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter ;wire [0:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg ;wire [128:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_005|saved_grant ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_018|src_data ;wire [3:0] \m_x|control_l_r ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|fsm_info|readdata ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_016|saved_grant ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|saved_grant ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [7:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_020|saved_grant ;wire [152:0] \u0|mm_interconnect_0|cmd_mux|src_payload ;wire [8:0] \A_SPW_TOP|tx_data|data_out ;wire [7:0] \u0|timecode_tx_data|data_out ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_002|saved_grant ;wire [3:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec_p ;wire [0:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_ARVALID ;wire [7:0] \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|divclk ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter ;wire [128:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [4:0] \u0|led_pio_test|data_out ;wire [31:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [0:0] \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_017|saved_grant ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_019|saved_grant ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [128:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [13:0] \u0|data_info|read_mux_out ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_AWBURST ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [31:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|saved_grant ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [31:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [31:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WVALID ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_ARADDR ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WLAST ;wire [128:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [3:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [5:0] \A_SPW_TOP|rx_data|counter ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_ARLEN ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|saved_grant ;wire [3:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_RREADY ;wire [7:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_012|saved_grant ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|saved_grant ;wire [0:21] \A_SPW_TOP|tx_data|mem_rtl_0_bypass ;wire [31:0] \u0|data_info|readdata ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|fifo_full_rx_status|readdata ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_ARID ;wire [3:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_013|saved_grant ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|saved_grant ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_AWID ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_WSTRB ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus ;wire [8:0] \A_SPW_TOP|rx_data|data_out ;wire [2:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_010|src_payload ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [3:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [31:0] \u0|timecode_ready_rx|readdata ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_ARSIZE ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_AWVALID ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [3:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_ARBURST ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter ;wire [31:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre ;wire [128:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_011|src_data ;wire [128:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_AWSIZE ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|saved_grant ;wire [128:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [7:0] \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_006|saved_grant ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_p_r ;wire [7:0] \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec ;wire [128:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [31:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre ;wire [2:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_AWADDR ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter ;wire [0:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used ;wire [7:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [31:0] \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre ;wire [128:0] \u0|mm_interconnect_0|rsp_mux|src_data ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_rst_n ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter ;wire [8:0] \u0|write_data_fifo_tx|data_out ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter ;wire [3:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [0:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_003|saved_grant ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_021|saved_grant ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [7:0] \u0|timecode_rx|read_mux_out ;wire [3:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre ;wire [13:0] \A_SPW_TOP|SPW|TX|timecode_s ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control ;wire [31:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_AWLEN ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre ;wire [31:0] \u0|hps_0|fpga_interfaces|h2f_WDATA ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_014|src_payload ;wire [1:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre ;wire [2:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [128:0] \u0|mm_interconnect_0|rsp_mux_001|src_data ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [5:0] \m_x|counter_neg ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_009|src_data ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|saved_grant ;wire [6:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_008|src_data ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_008|src_payload ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_004|src_data ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg ;wire [5:0] \A_SPW_TOP|rx_data|credit_counter ;wire [7:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [3:0] \A_SPW_TOP|SPW|TX|global_counter_transfer ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_004|src_payload ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [13:0] \m_x|info ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [128:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_receive ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_018|src_payload ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_015|src_data ;wire [5:0] \A_SPW_TOP|tx_data|counter ;wire [128:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_015|src_payload ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [128:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_014|src_data ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [3:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_010|src_data ;wire [2:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [9:0] \A_SPW_TOP|SPW|RX|timecode ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [31:0] \u0|counter_rx_fifo|readdata ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after128us ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [9:0] \m_x|timecode ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|counter_tx_fifo|readdata ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_001|saved_grant ;wire [31:0] \u0|write_data_fifo_tx|readdata ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [0:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [5:0] \A_SPW_TOP|tx_data|rd_ptr ;wire [0:0] \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg ;wire [31:0] \u0|timecode_tx_data|readdata ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [2:0] \u0|clock_sel|data_out ;wire [31:0] \u0|data_flag_rx|readdata ;wire [31:0] \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre ;wire [31:0] \u0|led_pio_test|readdata ;wire [7:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [31:0] \u0|timecode_rx|readdata ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [31:0] \u0|fifo_empty_tx_status|readdata ;wire [31:0] \u0|fifo_empty_rx_status|readdata ;wire [31:0] \u0|timecode_tx_ready|readdata ;wire [7:0] \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire ;wire [8:0] \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag ;wire [1:0] \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_007|src_payload ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [7:0] \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [8:0] \u0|data_flag_rx|read_mux_out ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|saved_grant ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_BREADY ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ;wire [127:0] \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ;wire [15:0] \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ;wire [39:0] \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;wire [39:0] \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus ;assign \u0|hps_0|fpga_interfaces|tpiu~trace_data = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [0];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [1];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [2];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [3];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [4];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [5];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [6];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [7];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [8];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [9];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [10];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [11];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [12];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [13];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [14];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [15];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [16];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [17];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [18];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [19];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [20];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [21];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [22];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [23];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [24];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [25];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [26];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [27];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [28];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [29];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [30];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [31];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [0];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [1];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [2];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [20] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [20];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [21] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [21];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [22] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [22];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [23] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [23];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [24] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [24];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [25] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [25];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [26] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [26];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [27] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [27];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [28] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [28];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [29] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [29];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [4] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [5] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [6] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [7] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [8] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus [2];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a1 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a2 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a3 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a4 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [4];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a5 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [5];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a6 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [6];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a7 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [7];assign \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a8 = \A_SPW_TOP|tx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [8];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0~portbdataout = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [0];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a1 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [1];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a2 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [2];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a3 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [3];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a4 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [4];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a5 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [5];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a6 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [6];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a7 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [7];assign \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a8 = \A_SPW_TOP|rx_data|mem_rtl_0|auto_generated|ram_block1a0_PORTBDATAOUT_bus [8];// Location: IOOBUF_X68_Y10_N96cyclonev_io_obuf \LED[5]~output (.i(\db_system_spwulight_b|PB_down~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[5]),.obar());// synopsys translate_offdefparam \LED[5]~output .bus_hold = "false";defparam \LED[5]~output .open_drain_output = "false";defparam \LED[5]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N56cyclonev_io_obuf \LED[7]~output (.i(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[7]),.obar());// synopsys translate_offdefparam \LED[7]~output .bus_hold = "false";defparam \LED[7]~output .open_drain_output = "false";defparam \LED[7]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X65_Y0_N36cyclonev_io_obuf \dout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(dout_a),.obar(\dout_a(n) ));// synopsys translate_offdefparam \dout_a~output .bus_hold = "false";defparam \dout_a~output .open_drain_output = "false";defparam \dout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X53_Y0_N36cyclonev_io_obuf \sout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(sout_a),.obar(\sout_a(n) ));// synopsys translate_offdefparam \sout_a~output .bus_hold = "false";defparam \sout_a~output .open_drain_output = "false";defparam \sout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N22cyclonev_io_obuf \LED[0]~output (.i(\u0|led_pio_test|data_out [0]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[0]),.obar());// synopsys translate_offdefparam \LED[0]~output .bus_hold = "false";defparam \LED[0]~output .open_drain_output = "false";defparam \LED[0]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N39cyclonev_io_obuf \LED[1]~output (.i(\u0|led_pio_test|data_out [1]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[1]),.obar());// synopsys translate_offdefparam \LED[1]~output .bus_hold = "false";defparam \LED[1]~output .open_drain_output = "false";defparam \LED[1]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N5cyclonev_io_obuf \LED[2]~output (.i(\u0|led_pio_test|data_out [2]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[2]),.obar());// synopsys translate_offdefparam \LED[2]~output .bus_hold = "false";defparam \LED[2]~output .open_drain_output = "false";defparam \LED[2]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N22cyclonev_io_obuf \LED[3]~output (.i(\u0|led_pio_test|data_out [3]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[3]),.obar());// synopsys translate_offdefparam \LED[3]~output .bus_hold = "false";defparam \LED[3]~output .open_drain_output = "false";defparam \LED[3]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y10_N79cyclonev_io_obuf \LED[4]~output (.i(\u0|led_pio_test|data_out [4]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[4]),.obar());// synopsys translate_offdefparam \LED[4]~output .bus_hold = "false";defparam \LED[4]~output .open_drain_output = "false";defparam \LED[4]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N5cyclonev_io_obuf \LED[6]~output (.i(gnd),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[6]),.obar());// synopsys translate_offdefparam \LED[6]~output .bus_hold = "false";defparam \LED[6]~output .open_drain_output = "false";defparam \LED[6]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOIBUF_X38_Y0_N1cyclonev_io_ibuf \FPGA_CLK1_50~input (.i(FPGA_CLK1_50),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\FPGA_CLK1_50~input_o ));// synopsys translate_offdefparam \FPGA_CLK1_50~input .bus_hold = "false";defparam \FPGA_CLK1_50~input .simulate_z_as = "z";// synopsys translate_on// Location: CLKCTRL_G5cyclonev_clkena \FPGA_CLK1_50~inputCLKENA0 (.inclk(\FPGA_CLK1_50~input_o ),.ena(vcc),.outclk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \FPGA_CLK1_50~inputCLKENA0 .clock_type = "global clock";defparam \FPGA_CLK1_50~inputCLKENA0 .disable_mode = "low";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_mode = "always enabled";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_power_up = "high";defparam \FPGA_CLK1_50~inputCLKENA0 .test_syn = "high";// synopsys translate_on// Location: IOIBUF_X46_Y0_N52cyclonev_io_ibuf \KEY[1]~input (.i(KEY[1]),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\KEY[1]~input_o ));// synopsys translate_offdefparam \KEY[1]~input .bus_hold = "false";defparam \KEY[1]~input .simulate_z_as = "z";// synopsys translate_on// Location: MLABCELL_X47_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|PB_down~0 (// Equation(s):// \db_system_spwulight_b|PB_down~0_combout = !\KEY[1]~input_o.dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|PB_down~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|PB_down~0 .extended_lut = "off";defparam \db_system_spwulight_b|PB_down~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \db_system_spwulight_b|PB_down~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|Add0~61 (// Equation(s):// \db_system_spwulight_b|Add0~61_sumout = SUM(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))// \db_system_spwulight_b|Add0~62 = CARRY(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~61_sumout ),.cout(\db_system_spwulight_b|Add0~62 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~61 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~61 .lut_mask = 64'h00000000000000FF;defparam \db_system_spwulight_b|Add0~61 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|counter~16 (// Equation(s):// \db_system_spwulight_b|counter~16_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~61_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~61_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~16 .extended_lut = "off";defparam \db_system_spwulight_b|counter~16 .lut_mask = 64'h00AA00AA00AA00AA;defparam \db_system_spwulight_b|counter~16 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N6cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~0 (// Equation(s):// \db_system_spwulight_b|LessThan0~0_combout = ( !\db_system_spwulight_b|counter [9] & ( (!\db_system_spwulight_b|counter [10] & (!\db_system_spwulight_b|counter [11] & (!\db_system_spwulight_b|counter [13] & !\db_system_spwulight_b|counter [12]))) ) ).dataa(!\db_system_spwulight_b|counter [10]),.datab(!\db_system_spwulight_b|counter [11]),.datac(!\db_system_spwulight_b|counter [13]),.datad(!\db_system_spwulight_b|counter [12]),.datae(gnd),.dataf(!\db_system_spwulight_b|counter [9]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~0 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~0 .lut_mask = 64'h8000800000000000;defparam \db_system_spwulight_b|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~1 (// Equation(s):// \db_system_spwulight_b|LessThan0~1_combout = ( \db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [7] & \db_system_spwulight_b|counter [8]) ) ) # ( !\db_system_spwulight_b|counter [5] & ( (\db_system_spwulight_b|counter [7] &// (\db_system_spwulight_b|counter [8] & ((\db_system_spwulight_b|counter [4]) # (\db_system_spwulight_b|counter [6])))) ) ).dataa(!\db_system_spwulight_b|counter [6]),.datab(!\db_system_spwulight_b|counter [7]),.datac(!\db_system_spwulight_b|counter [4]),.datad(!\db_system_spwulight_b|counter [8]),.datae(gnd),.dataf(!\db_system_spwulight_b|counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~1 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~1 .lut_mask = 64'h0013001300330033;defparam \db_system_spwulight_b|LessThan0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N21cyclonev_lcell_comb \db_system_spwulight_b|counter[0]~1 (// Equation(s):// \db_system_spwulight_b|counter[0]~1_combout = ( \KEY[1]~input_o ) # ( !\KEY[1]~input_o & ( (!\db_system_spwulight_b|counter [15] & (\db_system_spwulight_b|LessThan0~0_combout & (!\db_system_spwulight_b|LessThan0~1_combout &// !\db_system_spwulight_b|counter [14]))) ) ).dataa(!\db_system_spwulight_b|counter [15]),.datab(!\db_system_spwulight_b|LessThan0~0_combout ),.datac(!\db_system_spwulight_b|LessThan0~1_combout ),.datad(!\db_system_spwulight_b|counter [14]),.datae(gnd),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter[0]~1 .extended_lut = "off";defparam \db_system_spwulight_b|counter[0]~1 .lut_mask = 64'h20002000FFFFFFFF;defparam \db_system_spwulight_b|counter[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N59dffeas \db_system_spwulight_b|counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~16_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [0]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[0] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|Add0~57 (// Equation(s):// \db_system_spwulight_b|Add0~57_sumout = SUM(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 ))// \db_system_spwulight_b|Add0~58 = CARRY(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~62 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~57_sumout ),.cout(\db_system_spwulight_b|Add0~58 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~57 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~57 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~57 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|counter~15 (// Equation(s):// \db_system_spwulight_b|counter~15_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~57_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~57_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~15 .extended_lut = "off";defparam \db_system_spwulight_b|counter~15 .lut_mask = 64'h0A0A0A0A0A0A0A0A;defparam \db_system_spwulight_b|counter~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N56dffeas \db_system_spwulight_b|counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~15_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [1]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[1] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N6cyclonev_lcell_comb \db_system_spwulight_b|Add0~53 (// Equation(s):// \db_system_spwulight_b|Add0~53_sumout = SUM(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 ))// \db_system_spwulight_b|Add0~54 = CARRY(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~58 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~53_sumout ),.cout(\db_system_spwulight_b|Add0~54 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~53 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~53 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~53 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N51cyclonev_lcell_comb \db_system_spwulight_b|counter~14 (// Equation(s):// \db_system_spwulight_b|counter~14_combout = ( \db_system_spwulight_b|Add0~53_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~53_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~14 .extended_lut = "off";defparam \db_system_spwulight_b|counter~14 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N53dffeas \db_system_spwulight_b|counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~14_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [2]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[2] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|Add0~49 (// Equation(s):// \db_system_spwulight_b|Add0~49_sumout = SUM(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 ))// \db_system_spwulight_b|Add0~50 = CARRY(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 )).dataa(!\db_system_spwulight_b|counter [3]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~54 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~49_sumout ),.cout(\db_system_spwulight_b|Add0~50 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~49 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~49 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~49 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~13 (// Equation(s):// \db_system_spwulight_b|counter~13_combout = ( \db_system_spwulight_b|Add0~49_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~49_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~13 .extended_lut = "off";defparam \db_system_spwulight_b|counter~13 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N50dffeas \db_system_spwulight_b|counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~13_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [3]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[3] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|Add0~37 (// Equation(s):// \db_system_spwulight_b|Add0~37_sumout = SUM(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 ))// \db_system_spwulight_b|Add0~38 = CARRY(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [4]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~50 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~37_sumout ),.cout(\db_system_spwulight_b|Add0~38 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~37 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~37 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~37 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|counter~10 (// Equation(s):// \db_system_spwulight_b|counter~10_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~37_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~37_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~10 .extended_lut = "off";defparam \db_system_spwulight_b|counter~10 .lut_mask = 64'h0A0A0A0A0A0A0A0A;defparam \db_system_spwulight_b|counter~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N2dffeas \db_system_spwulight_b|counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~10_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [4]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[4] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N15cyclonev_lcell_comb \db_system_spwulight_b|Add0~41 (// Equation(s):// \db_system_spwulight_b|Add0~41_sumout = SUM(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 ))// \db_system_spwulight_b|Add0~42 = CARRY(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [5]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~38 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~41_sumout ),.cout(\db_system_spwulight_b|Add0~42 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~41 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~41 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~41 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N15cyclonev_lcell_comb \db_system_spwulight_b|counter~11 (// Equation(s):// \db_system_spwulight_b|counter~11_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~41_sumout ) ).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~41_sumout ),.datad(gnd),.datae(gnd),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~11 .extended_lut = "off";defparam \db_system_spwulight_b|counter~11 .lut_mask = 64'h0F0F0F0F00000000;defparam \db_system_spwulight_b|counter~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N17dffeas \db_system_spwulight_b|counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~11_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [5]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[5] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|Add0~45 (// Equation(s):// \db_system_spwulight_b|Add0~45_sumout = SUM(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 ))// \db_system_spwulight_b|Add0~46 = CARRY(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [6]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~42 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~45_sumout ),.cout(\db_system_spwulight_b|Add0~46 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~45 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~45 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~45 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|counter~12 (// Equation(s):// \db_system_spwulight_b|counter~12_combout = ( \db_system_spwulight_b|Add0~45_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~45_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~12 .extended_lut = "off";defparam \db_system_spwulight_b|counter~12 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~12 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N5dffeas \db_system_spwulight_b|counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~12_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [6]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[6] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N21cyclonev_lcell_comb \db_system_spwulight_b|Add0~29 (// Equation(s):// \db_system_spwulight_b|Add0~29_sumout = SUM(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 ))// \db_system_spwulight_b|Add0~30 = CARRY(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [7]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~46 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~29_sumout ),.cout(\db_system_spwulight_b|Add0~30 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~29 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~29 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~29 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|counter~8 (// Equation(s):// \db_system_spwulight_b|counter~8_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~29_sumout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~29_sumout ),.datae(gnd),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~8 .extended_lut = "off";defparam \db_system_spwulight_b|counter~8 .lut_mask = 64'h00FF00FF00000000;defparam \db_system_spwulight_b|counter~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N11dffeas \db_system_spwulight_b|counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~8_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [7]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[7] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N24cyclonev_lcell_comb \db_system_spwulight_b|Add0~33 (// Equation(s):// \db_system_spwulight_b|Add0~33_sumout = SUM(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 ))// \db_system_spwulight_b|Add0~34 = CARRY(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [8]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~30 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~33_sumout ),.cout(\db_system_spwulight_b|Add0~34 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~33 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~33 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~33 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|counter~9 (// Equation(s):// \db_system_spwulight_b|counter~9_combout = ( \db_system_spwulight_b|Add0~33_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~33_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~9 .extended_lut = "off";defparam \db_system_spwulight_b|counter~9 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N59dffeas \db_system_spwulight_b|counter[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~9_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [8]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[8] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|Add0~9 (// Equation(s):// \db_system_spwulight_b|Add0~9_sumout = SUM(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 ))// \db_system_spwulight_b|Add0~10 = CARRY(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [9]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~34 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~9_sumout ),.cout(\db_system_spwulight_b|Add0~10 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~9 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~9 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~3 (// Equation(s):// \db_system_spwulight_b|counter~3_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~9_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~9_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~3 .extended_lut = "off";defparam \db_system_spwulight_b|counter~3 .lut_mask = 64'h0A0A0A0A0A0A0A0A;defparam \db_system_spwulight_b|counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N50dffeas \db_system_spwulight_b|counter[9] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~3_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [9]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[9] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|Add0~13 (// Equation(s):// \db_system_spwulight_b|Add0~13_sumout = SUM(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 ))// \db_system_spwulight_b|Add0~14 = CARRY(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [10]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~10 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~13_sumout ),.cout(\db_system_spwulight_b|Add0~14 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~13 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N51cyclonev_lcell_comb \db_system_spwulight_b|counter~4 (// Equation(s):// \db_system_spwulight_b|counter~4_combout = ( \db_system_spwulight_b|Add0~13_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~13_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~4 .extended_lut = "off";defparam \db_system_spwulight_b|counter~4 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N53dffeas \db_system_spwulight_b|counter[10] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~4_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [10]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[10] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[10] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|Add0~17 (// Equation(s):// \db_system_spwulight_b|Add0~17_sumout = SUM(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 ))// \db_system_spwulight_b|Add0~18 = CARRY(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [11]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~14 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~17_sumout ),.cout(\db_system_spwulight_b|Add0~18 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~17 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~17 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|counter~5 (// Equation(s):// \db_system_spwulight_b|counter~5_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~17_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~17_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~5 .extended_lut = "off";defparam \db_system_spwulight_b|counter~5 .lut_mask = 64'h00AA00AA00AA00AA;defparam \db_system_spwulight_b|counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N44dffeas \db_system_spwulight_b|counter[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~5_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [11]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[11] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[11] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|Add0~21 (// Equation(s):// \db_system_spwulight_b|Add0~21_sumout = SUM(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 ))// \db_system_spwulight_b|Add0~22 = CARRY(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [12]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~18 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~21_sumout ),.cout(\db_system_spwulight_b|Add0~22 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~21 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~21 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|counter~6 (// Equation(s):// \db_system_spwulight_b|counter~6_combout = ( \db_system_spwulight_b|Add0~21_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~21_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~6 .extended_lut = "off";defparam \db_system_spwulight_b|counter~6 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N47dffeas \db_system_spwulight_b|counter[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~6_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [12]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[12] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N39cyclonev_lcell_comb \db_system_spwulight_b|Add0~25 (// Equation(s):// \db_system_spwulight_b|Add0~25_sumout = SUM(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 ))// \db_system_spwulight_b|Add0~26 = CARRY(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [13]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~22 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~25_sumout ),.cout(\db_system_spwulight_b|Add0~26 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~25 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~25 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|counter~7 (// Equation(s):// \db_system_spwulight_b|counter~7_combout = ( \db_system_spwulight_b|Add0~25_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~25_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~7 .extended_lut = "off";defparam \db_system_spwulight_b|counter~7 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N56dffeas \db_system_spwulight_b|counter[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~7_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [13]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[13] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|Add0~1 (// Equation(s):// \db_system_spwulight_b|Add0~1_sumout = SUM(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 ))// \db_system_spwulight_b|Add0~2 = CARRY(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [14]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~26 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~1_sumout ),.cout(\db_system_spwulight_b|Add0~2 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~1 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|counter~0 (// Equation(s):// \db_system_spwulight_b|counter~0_combout = ( \db_system_spwulight_b|Add0~1_sumout & ( !\KEY[1]~input_o ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\db_system_spwulight_b|Add0~1_sumout ),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~0 .extended_lut = "off";defparam \db_system_spwulight_b|counter~0 .lut_mask = 64'h0000FFFF00000000;defparam \db_system_spwulight_b|counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N29dffeas \db_system_spwulight_b|counter[14] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [14]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[14] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[14] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|Add0~5 (// Equation(s):// \db_system_spwulight_b|Add0~5_sumout = SUM(( \db_system_spwulight_b|counter [15] ) + ( GND ) + ( \db_system_spwulight_b|Add0~2 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [15]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~2 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~5_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~5 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~5 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|counter~2 (// Equation(s):// \db_system_spwulight_b|counter~2_combout = ( \db_system_spwulight_b|Add0~5_sumout & ( !\KEY[1]~input_o ) ).dataa(gnd),.datab(gnd),.datac(!\KEY[1]~input_o ),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~5_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~2 .extended_lut = "off";defparam \db_system_spwulight_b|counter~2 .lut_mask = 64'h00000000F0F0F0F0;defparam \db_system_spwulight_b|counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N38dffeas \db_system_spwulight_b|counter[15] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~2_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[0]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [15]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[15] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[15] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~0 (// Equation(s):// \db_system_spwulight_b|aux_pb~0_combout = ( \db_system_spwulight_b|LessThan0~1_combout ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( ((!\db_system_spwulight_b|LessThan0~0_combout ) # ((\db_system_spwulight_b|counter [14]) # (\KEY[1]~input_o )))// # (\db_system_spwulight_b|counter [15]) ) ).dataa(!\db_system_spwulight_b|counter [15]),.datab(!\db_system_spwulight_b|LessThan0~0_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [14]),.datae(gnd),.dataf(!\db_system_spwulight_b|LessThan0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|aux_pb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb~0 .extended_lut = "off";defparam \db_system_spwulight_b|aux_pb~0 .lut_mask = 64'hDFFFDFFFFFFFFFFF;defparam \db_system_spwulight_b|aux_pb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N34dffeas \db_system_spwulight_b|PB_down (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|PB_down~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|aux_pb~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|PB_down~q ),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|PB_down .is_wysiwyg = "true";defparam \db_system_spwulight_b|PB_down .power_up = "low";// synopsys translate_on// Location: PLLREFCLKSELECT_X68_Y7_N0cyclonev_pll_refclk_select \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT (.adjpllin(gnd),.cclk(gnd),.coreclkin(gnd),.extswitch(gnd),.iqtxrxclkin(gnd),.plliqclkin(gnd),.rxiqclkin(gnd),.clkin({gnd,gnd,gnd,\FPGA_CLK1_50~input_o }),.refiqclk(2'b00),.clk0bad(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ),.clk1bad(),.clkout(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.extswitchbuf(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.pllclksel());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_auto_clk_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_edge = "both_edges";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_sw_dly = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_0_src = "clk_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_1_src = "clk_1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_manu_clk_sw_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_sw_refclk_src = "clk_0";// synopsys translate_on// Location: MLABCELL_X47_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~1 (// Equation(s):// \db_system_spwulight_b|aux_pb~1_combout = !\KEY[1]~input_o.dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|aux_pb~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb~1 .extended_lut = "off";defparam \db_system_spwulight_b|aux_pb~1 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \db_system_spwulight_b|aux_pb~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N32dffeas \db_system_spwulight_b|aux_pb (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|aux_pb~1_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|aux_pb~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|aux_pb~q ),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb .is_wysiwyg = "true";defparam \db_system_spwulight_b|aux_pb .power_up = "low";// synopsys translate_on// Location: FRACTIONALPLL_X68_Y1_N0cyclonev_fractional_pll \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll (.coreclkfb(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.ecnc1test(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.ecnc2test(gnd),.fbclkfpll(gnd),.lvdsfbin(gnd),.nresync(!\db_system_spwulight_b|aux_pb~q ),.pfden(vcc),.refclkin(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdonein(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.zdb(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fbclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.fblvdsout(),.lock(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.mcntout(),.plniotribuf(),.shiftdoneout(),.tclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.mhi(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ),.vcoph(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .dsm_accumulator_reset_value = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .forcelock = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .mimic_fbclk_type = "none";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .nreset_invert = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_atb = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_bwctrl = 4000;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cmp_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_comp = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_current = 10;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ctrl_override_setting = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_dither = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_out_sel = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_reset = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_test_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_enable = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_1 = "glb";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_2 = "m_cnt";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_carry_out = 32;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division_string = "1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_value_ready = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lf_testen = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_cfg = 25;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_test = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_hi_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_lo_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_hi_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_lo_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ref_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_reg_boost = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_regulator_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ripplecap_ctrl = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_slf_rst = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_mux_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_sel = "n_src";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_test_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testdn_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testup_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_unlock_fltr_cfg = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_div = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph0_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph1_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph2_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph3_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph4_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph5_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph6_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph7_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vctrl_test_voltage = 750;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .reference_clock_frequency = "100.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccm1g_tap = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccr_pd = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vcodiv_override = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .fractional_pll_index = 0;// synopsys translate_on// Location: PLLRECONFIG_X68_Y5_N0cyclonev_pll_reconfig \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG (.atpgmode(gnd),.clk(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fpllcsrtest(gnd),.iocsrclkin(gnd),.iocsrdatain(gnd),.iocsren(gnd),.iocsrrstn(gnd),.mdiodis(vcc),.phaseen(gnd),.read(gnd),.rstn(vcc),.scanen(gnd),.sershiftload(vcc),.shiftdonei(gnd),.updn(gnd),.write(gnd),.addr(6'b000000),.byteen(2'b00),.cntsel(5'b00000),.din(16'b0000000000000000),.mhi({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0]}),.blockselect(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ),.iocsrdataout(),.iocsrenbuf(),.iocsrrstnbuf(),.phasedone(),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftenm(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.dout(),.dprioout(),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG .fractional_pll_index = 0;// synopsys translate_on// Location: PLLOUTPUTCOUNTER_X68_Y2_N1cyclonev_pll_output_counter \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter (.cascadein(gnd),.nen0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.shift0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdone0i(gnd),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [2]),.tclk0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.up0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.vco0ph({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0]}),.cascadeout(\u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire [0]),.divclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.shiftdone0o());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .cnt_fpll_src = "fpll_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_bypass_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_hi_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_lo_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_odd_div_even_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .duty_cycle = 50;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .phase_shift = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .fractional_pll_index = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_counter_index = 2;// synopsys translate_on// Location: CLKCTRL_G11cyclonev_clkena \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 (.inclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.ena(vcc),.outclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .clock_type = "global clock";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .disable_mode = "low";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: LABCELL_X27_Y1_N15cyclonev_lcell_comb \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y1_N17dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y1_N14dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y1_N38dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: CLKCTRL_G6cyclonev_clkena \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (.inclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.ena(vcc),.outclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .clock_type = "global clock";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .disable_mode = "low";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_power_up = "high";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X23_Y19_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y18_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y18_N52dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y20_N56dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y23_N9cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y23_N11dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: FF_X18_Y25_N20dffeas \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y27_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y27_N56dffeas \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0].dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y32_N54cyclonev_lcell_comb \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: HPSINTERFACECLOCKSRESETS_X32_Y50_N111cyclonev_hps_interface_clocks_resets \u0|hps_0|fpga_interfaces|clocks_resets (.f2h_cold_rst_req_n(vcc),.f2h_dbg_rst_req_n(vcc),.f2h_pending_rst_ack(vcc),.f2h_periph_ref_clk(gnd),.f2h_sdram_ref_clk(gnd),.f2h_warm_rst_req_n(vcc),.ptp_ref_clk(gnd),.h2f_cold_rst_n(\u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ),.h2f_pending_rst_req_n(),.h2f_rst_n(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.h2f_user0_clk(),.h2f_user1_clk(),.h2f_user2_clk());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user0_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user1_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user2_clk_freq = 100;// synopsys translate_on// Location: CLKCTRL_G10cyclonev_clkena \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 (.inclk(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.ena(vcc),.outclk(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .clock_type = "global clock";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .disable_mode = "low";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X30_Y32_N56dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y32_N59dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y32_N17dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout = ( \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & \u0|mm_interconnect_0|rsp_mux_001|src_payload [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .lut_mask = 64'h00000000000F000F;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y30_N55dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y28_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y28_N26dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout = !\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout.dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y24_N33cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) # (\u0|hps_0|fpga_interfaces|h2f_BREADY [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_RREADY// [0] & ( (\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datad(!\u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .lut_mask = 64'h000F000FFF0FFF0F;defparam \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y24_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y29_N20dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y27_N20dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y22_N32dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y29_N18cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout & ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .lut_mask = 64'h00FF00FFF0F0F0F0;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y29_N20dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable .power_up = "low";// synopsys translate_on// Location: FF_X28_Y21_N1dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal7~0_combout = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|hps_0|fpga_interfaces|h2f_ARADDR [18]).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal7~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal7~0 .lut_mask = 64'h00AA00AA00AA00AA;defparam \u0|mm_interconnect_0|router_001|Equal7~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal10~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal10~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|mm_interconnect_0|router_001|Equal2~0_combout &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal7~0_combout ))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal10~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal10~0 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|router_001|Equal10~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N28dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y27_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal10~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (// \u0|mm_interconnect_0|router_001|Equal10~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .lut_mask = 64'h0000330000003333;defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y16_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N1dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N29dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter// [0] & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter// [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N59dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y17_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ) )// ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33F733F733FF33FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0])))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0707070707000700;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h1F1F1F1F00000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N41dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]))))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1] $ (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h731F731F731F731F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y17_N17dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y17_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y17_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h1111111111111111;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N20dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h00005F5F00000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFF8F807F70;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $ (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )// # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0AF50AF54EE44EE4;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y17_N2dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0A00F5FF4E44E4EE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y17_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h01DD01DD00CC00CC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N56dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) )// ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) )// ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) )// ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h0000F0F50005F0F5;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFAC5CAC5C;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y17_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & (// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h030003FF030003FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y17_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0] ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0F000F00;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N53dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y17_N8dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h202F202F707F707F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N23dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y17_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000B78484B7;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N14dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y17_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h33CC33CCCCCCCCCC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y17_N26dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h00000F0F00F00FFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N20dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y17_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q $ (((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q// ))))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000A5CC0FCC;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N2dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N11dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y17_N53dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y17_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y17_N59dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout )) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0