URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [simulation/] [modelsim/] [spw_fifo_ulight.vo] - Rev 35
Go to most recent revision | Compare with Previous | Blame | View Log
// Copyright (C) 2017 Intel Corporation. All rights reserved.// Your use of Intel Corporation's design tools, logic functions// and other software and tools, and its AMPP partner logic// functions, and any output files from any of the foregoing// (including device programming or simulation files), and any// associated documentation or information are expressly subject// to the terms and conditions of the Intel Program License// Subscription Agreement, the Intel Quartus Prime License Agreement,// the Intel MegaCore Function License Agreement, or other// applicable license agreement, including, without limitation,// that your use is for the sole purpose of programming logic// devices manufactured by Intel and sold by Intel or its// authorized distributors. Please refer to the applicable// agreement for further details.// VENDOR "Altera"// PROGRAM "Quartus Prime"// VERSION "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition"// DATE "09/15/2017 08:19:18"//// Device: Altera 5CSEMA4U23C6 Package UFBGA672////// This Verilog file should be used for ModelSim-Altera (Verilog) only//`timescale 1 ps/ 1 psmodule SPW_ULIGHT_FIFO (\dout_a(n) ,\sout_a(n) ,\din_a(n) ,\sin_a(n) ,FPGA_CLK1_50,KEY,din_a,sin_a,dout_a,sout_a,LED);output \dout_a(n) ;output \sout_a(n) ;input \din_a(n) ;input \sin_a(n) ;input FPGA_CLK1_50;input [1:0] KEY;input din_a;input sin_a;output dout_a;output sout_a;output [7:0] LED;// Design Ports Information// dout_a => Location: PIN_AG28, I/O Standard: LVDS, Current Strength: Default// sout_a => Location: PIN_AF20, I/O Standard: LVDS, Current Strength: Default// LED[5] => Location: PIN_AE26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[7] => Location: PIN_AA23, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[0] => Location: PIN_W15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[1] => Location: PIN_AA24, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[2] => Location: PIN_V16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[3] => Location: PIN_V15, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// LED[4] => Location: PIN_AF26, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// KEY[0] => Location: PIN_AH17, I/O Standard: 3.3-V LVTTL, Current Strength: Default// LED[6] => Location: PIN_Y16, I/O Standard: 3.3-V LVTTL, Current Strength: 16mA// FPGA_CLK1_50 => Location: PIN_Y13, I/O Standard: 3.3-V LVTTL, Current Strength: Default// KEY[1] => Location: PIN_AH16, I/O Standard: 3.3-V LVTTL, Current Strength: Default// din_a => Location: PIN_Y15, I/O Standard: LVDS, Current Strength: Default// sin_a => Location: PIN_AE20, I/O Standard: LVDS, Current Strength: Default// dout_a(n) => Location: PIN_AH27, I/O Standard: LVDS, Current Strength: Default// sout_a(n) => Location: PIN_AG20, I/O Standard: LVDS, Current Strength: Default// din_a(n) => Location: PIN_AA15, I/O Standard: LVDS, Current Strength: Default// sin_a(n) => Location: PIN_AD20, I/O Standard: LVDS, Current Strength: Defaultwire gnd;wire vcc;wire unknown;assign gnd = 1'b0;assign vcc = 1'b1;assign unknown = 1'bx;tri1 devclrn;tri1 devpor;tri1 devoe;wire \u0|hps_0|fpga_interfaces|tpiu~trace_data ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 ;wire \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 ;wire \u0|hps_0|fpga_interfaces|boot_from_fpga~fake_dout ;wire \u0|hps_0|fpga_interfaces|fpga2hps~arready ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 ;wire \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 ;wire \u0|hps_0|fpga_interfaces|debug_apb~O_P_ADDR_31 ;wire \u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ;wire \KEY[0]~input_o ;wire \~QUARTUS_CREATED_GND~I_combout ;wire \FPGA_CLK1_50~input_o ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ;wire \FPGA_CLK1_50~inputCLKENA0_outclk ;wire \KEY[1]~input_o ;wire \db_system_spwulight_b|aux_pb~0_combout ;wire \db_system_spwulight_b|Add0~61_sumout ;wire \db_system_spwulight_b|counter~16_combout ;wire \db_system_spwulight_b|LessThan0~0_combout ;wire \db_system_spwulight_b|LessThan0~1_combout ;wire \db_system_spwulight_b|counter[13]~1_combout ;wire \db_system_spwulight_b|Add0~62 ;wire \db_system_spwulight_b|Add0~57_sumout ;wire \db_system_spwulight_b|counter~15_combout ;wire \db_system_spwulight_b|Add0~58 ;wire \db_system_spwulight_b|Add0~53_sumout ;wire \db_system_spwulight_b|counter~14_combout ;wire \db_system_spwulight_b|Add0~54 ;wire \db_system_spwulight_b|Add0~49_sumout ;wire \db_system_spwulight_b|counter~13_combout ;wire \db_system_spwulight_b|Add0~50 ;wire \db_system_spwulight_b|Add0~37_sumout ;wire \db_system_spwulight_b|counter~10_combout ;wire \db_system_spwulight_b|Add0~38 ;wire \db_system_spwulight_b|Add0~41_sumout ;wire \db_system_spwulight_b|counter~11_combout ;wire \db_system_spwulight_b|Add0~42 ;wire \db_system_spwulight_b|Add0~45_sumout ;wire \db_system_spwulight_b|counter~12_combout ;wire \db_system_spwulight_b|Add0~46 ;wire \db_system_spwulight_b|Add0~29_sumout ;wire \db_system_spwulight_b|counter~8_combout ;wire \db_system_spwulight_b|Add0~30 ;wire \db_system_spwulight_b|Add0~33_sumout ;wire \db_system_spwulight_b|counter~9_combout ;wire \db_system_spwulight_b|Add0~34 ;wire \db_system_spwulight_b|Add0~9_sumout ;wire \db_system_spwulight_b|counter~3_combout ;wire \db_system_spwulight_b|Add0~10 ;wire \db_system_spwulight_b|Add0~13_sumout ;wire \db_system_spwulight_b|counter~4_combout ;wire \db_system_spwulight_b|Add0~14 ;wire \db_system_spwulight_b|Add0~17_sumout ;wire \db_system_spwulight_b|counter~5_combout ;wire \db_system_spwulight_b|Add0~18 ;wire \db_system_spwulight_b|Add0~21_sumout ;wire \db_system_spwulight_b|counter~6_combout ;wire \db_system_spwulight_b|Add0~22 ;wire \db_system_spwulight_b|Add0~25_sumout ;wire \db_system_spwulight_b|counter~7_combout ;wire \db_system_spwulight_b|Add0~26 ;wire \db_system_spwulight_b|Add0~1_sumout ;wire \db_system_spwulight_b|counter~0_combout ;wire \db_system_spwulight_b|Add0~2 ;wire \db_system_spwulight_b|Add0~5_sumout ;wire \db_system_spwulight_b|counter~2_combout ;wire \db_system_spwulight_b|PB_down~0_combout ;wire \db_system_spwulight_b|aux_pb~q ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ;wire \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ;wire \u0|mm_interconnect_0|router|Equal15~1_combout ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ;wire \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ;wire \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal7~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal10~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ;wire \sin_a~input_o ;wire \din_a~input_o ;wire \A_SPW_TOP|SPW|RX|always3~0_combout ;wire \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ;wire \m_x|counter_neg[0]~feeder_combout ;wire \m_x|Selector2~0_combout ;wire \m_x|Selector1~0_combout ;wire \m_x|Selector4~0_combout ;wire \m_x|Selector4~1_combout ;wire \m_x|WideOr7~0_combout ;wire \m_x|Selector3~0_combout ;wire \m_x|control_bit_found~q ;wire \m_x|Selector0~1_combout ;wire \m_x|Selector0~0_combout ;wire \m_x|Equal1~0_combout ;wire \m_x|Selector0~2_combout ;wire \m_x|is_control~q ;wire \m_x|Selector3~1_combout ;wire \m_x|Selector5~1_combout ;wire \m_x|Selector5~0_combout ;wire \m_x|Selector5~2_combout ;wire \m_x|always2~0_combout ;wire \m_x|always1~0_combout ;wire \m_x|bit_c_0~q ;wire \m_x|bit_c_2~q ;wire \m_x|ready_control_p_r~0_combout ;wire \m_x|ready_control_p_r~q ;wire \m_x|control_l_r[2]~feeder_combout ;wire \m_x|info[12]~feeder_combout ;wire \m_x|ready_data_p_r~0_combout ;wire \m_x|ready_data_p~combout ;wire \m_x|ready_data_p_r~1_combout ;wire \m_x|ready_data_p_r~q ;wire \m_x|data_l_r[7]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ;wire \m_x|bit_c_1~feeder_combout ;wire \m_x|bit_c_1~q ;wire \m_x|bit_c_3~q ;wire \m_x|control[3]~feeder_combout ;wire \m_x|control_l_r[3]~feeder_combout ;wire \m_x|info[13]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|router_001|Equal13~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~3_combout ;wire \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal12~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router_001|Equal7~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal7~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~7_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router|Equal17~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal17~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal17~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ;wire \u0|mm_interconnect_0|router_001|Equal19~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|router|Equal13~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|router_001|Equal14~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210_combout ;wire \u0|mm_interconnect_0|router_001|Equal18~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal18~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|router_001|Equal3~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal11~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ;wire \u0|mm_interconnect_0|router_001|Equal9~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~10_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~4_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ;wire \u0|mm_interconnect_0|router_001|src_data[103]~5_combout ;wire \u0|mm_interconnect_0|router_001|Equal3~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~4_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~16_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_mux|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~214_combout ;wire \u0|mm_interconnect_0|router_001|Equal5~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_003|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~216_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_009|src1_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~211_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_demux_011|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|src_valid~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][116]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~212_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~201_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~55_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~205_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~54_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~204_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~206_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~199_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~200_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~203_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~202_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~20_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~197_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][115]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][115]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[115]~198_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~187_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~188_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~192_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~191_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~193_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~189_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~190_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~53_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~195_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~52_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~194_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[114]~196_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_011|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src1_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~182_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~181_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~177_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~178_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~183_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~179_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~180_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~51_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~185_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~50_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~184_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[113]~186_combout ;wire \u0|mm_interconnect_0|router|Equal21~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~173_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~171_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~167_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~168_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~7_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~169_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~170_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~172_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~7_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~49_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~175_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~17_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~48_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~174_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][112]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][112]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[112]~176_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~163_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~162_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~161_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~157_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~158_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~6_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~159_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~6_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~160_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~47_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~165_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~6_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~46_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][111]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~164_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[111]~166_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ;wire \u0|mm_interconnect_0|router|Equal7~9_combout ;wire \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_004|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~45_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~155_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~44_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~154_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~156_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~153_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~147_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~148_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~151_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~5_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~149_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~150_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[110]~152_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_021|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~139_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~140_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~43_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~145_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~42_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~144_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~146_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~142_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~137_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~138_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~141_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][109]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[109]~143_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_016|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~127_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~128_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~41_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~135_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~3_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~40_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~134_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~136_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~132_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~129_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~130_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~133_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][108]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][108]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[108]~131_combout ;wire \u0|mm_interconnect_0|router_001|Equal21~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src15_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~123_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~117_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~118_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~121_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~119_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~120_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~39_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~125_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~38_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~124_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~126_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][107]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][107]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[107]~122_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~113_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~112_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~109_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~110_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~107_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~108_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~111_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~36_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~114_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~37_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~115_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[106]~116_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~102_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~99_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~100_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~34_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~104_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~35_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~105_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~106_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~97_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~98_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~103_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][105]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][105]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[105]~101_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][12]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|src_payload~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector4~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector6~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector13~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~77_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector29~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[0]~9_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector5~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add3~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~78 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~73_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector28~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[1]~8_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~74 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~69_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector27~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[2]~7_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~70 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~65_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector26~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[3]~6_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add4~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector3~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder1~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector10~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|auto_start|always0~0_combout ;wire \u0|auto_start|data_out~q ;wire \A_SPW_TOP|SPW|FSM|Add1~6 ;wire \A_SPW_TOP|SPW|FSM|Add1~2 ;wire \A_SPW_TOP|SPW|FSM|Add1~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~30 ;wire \A_SPW_TOP|SPW|FSM|Add1~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~26 ;wire \A_SPW_TOP|SPW|FSM|Add1~22 ;wire \A_SPW_TOP|SPW|FSM|Add1~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~18 ;wire \A_SPW_TOP|SPW|FSM|Add1~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~14 ;wire \A_SPW_TOP|SPW|FSM|Add1~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~38 ;wire \A_SPW_TOP|SPW|FSM|Add1~34 ;wire \A_SPW_TOP|SPW|FSM|Add1~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~10 ;wire \A_SPW_TOP|SPW|FSM|Add1~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~13_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~46 ;wire \A_SPW_TOP|SPW|FSM|Add1~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~12_combout ;wire \A_SPW_TOP|rx_data|overflow_credit_error~feeder_combout ;wire \A_SPW_TOP|tx_reset_n~0_combout ;wire \A_SPW_TOP|SPW|RX|always1~0_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_1~q ;wire \A_SPW_TOP|SPW|RX|control_p_r[1]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|RX|control_bit_found~q ;wire \A_SPW_TOP|SPW|RX|Selector0~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector0~2_combout ;wire \A_SPW_TOP|SPW|RX|is_control~q ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_control_p_r~q ;wire \A_SPW_TOP|SPW|RX|ready_data_p~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p~combout ;wire \A_SPW_TOP|SPW|RX|ready_data~combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~0_combout ;wire \A_SPW_TOP|SPW|RX|ready_data_p_r~q ;wire \A_SPW_TOP|SPW|RX|last_is_control~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_control~q ;wire \A_SPW_TOP|SPW|RX|bit_c_0~q ;wire \A_SPW_TOP|SPW|RX|bit_c_2~q ;wire \A_SPW_TOP|SPW|RX|last_is_data~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_data~1_combout ;wire \A_SPW_TOP|SPW|RX|last_is_data~q ;wire \A_SPW_TOP|SPW|RX|rx_data_take~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_take~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_take~q ;wire \A_SPW_TOP|SPW|RX|rx_data_take_0~q ;wire \A_SPW_TOP|SPW|RX|rx_buffer_write~q ;wire \A_SPW_TOP|rx_data|rd_ptr[0]~0_combout ;wire \A_SPW_TOP|rx_data|Add4~1_sumout ;wire \A_SPW_TOP|rx_data|block_write~0_combout ;wire \A_SPW_TOP|rx_data|block_write~feeder_combout ;wire \A_SPW_TOP|rx_data|block_write~q ;wire \A_SPW_TOP|rx_data|always1~1_combout ;wire \A_SPW_TOP|rx_data|Add4~2 ;wire \A_SPW_TOP|rx_data|Add4~5_sumout ;wire \A_SPW_TOP|rx_data|Add4~6 ;wire \A_SPW_TOP|rx_data|Add4~9_sumout ;wire \A_SPW_TOP|rx_data|Add4~10 ;wire \A_SPW_TOP|rx_data|Add4~13_sumout ;wire \A_SPW_TOP|rx_data|Add4~14 ;wire \A_SPW_TOP|rx_data|Add4~17_sumout ;wire \A_SPW_TOP|rx_data|Add4~18 ;wire \A_SPW_TOP|rx_data|Add4~21_sumout ;wire \A_SPW_TOP|rx_data|Equal0~0_combout ;wire \A_SPW_TOP|rx_data|f_full~q ;wire \u0|mm_interconnect_0|cmd_mux_004|src_payload~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|data_read_en_rx|always0~0_combout ;wire \u0|data_read_en_rx|data_out~q ;wire \A_SPW_TOP|rx_data|block_read~0_combout ;wire \A_SPW_TOP|rx_data|block_read~q ;wire \A_SPW_TOP|rx_data|counter[5]~0_combout ;wire \A_SPW_TOP|rx_data|Equal1~0_combout ;wire \A_SPW_TOP|rx_data|f_empty~q ;wire \A_SPW_TOP|rx_data|always1~0_combout ;wire \A_SPW_TOP|rx_data|Add6~4_combout ;wire \A_SPW_TOP|rx_data|Add6~3_combout ;wire \A_SPW_TOP|rx_data|Add6~2_combout ;wire \A_SPW_TOP|rx_data|Add6~1_combout ;wire \A_SPW_TOP|rx_data|Add6~0_combout ;wire \A_SPW_TOP|rx_data|always2~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter[0]~13_combout ;wire \A_SPW_TOP|rx_data|always1~2_combout ;wire \A_SPW_TOP|rx_data|Add2~2_combout ;wire \A_SPW_TOP|rx_data|Add2~1_combout ;wire \A_SPW_TOP|rx_data|Add2~0_combout ;wire \A_SPW_TOP|rx_data|credit_counter~5_combout ;wire \A_SPW_TOP|rx_data|credit_counter~3_combout ;wire \A_SPW_TOP|rx_data|credit_counter[5]~1_combout ;wire \A_SPW_TOP|rx_data|credit_counter~4_combout ;wire \A_SPW_TOP|rx_data|credit_counter~2_combout ;wire \A_SPW_TOP|rx_data|credit_counter~7_combout ;wire \A_SPW_TOP|rx_data|credit_counter~8_combout ;wire \A_SPW_TOP|rx_data|credit_counter~6_combout ;wire \A_SPW_TOP|rx_data|credit_counter~0_combout ;wire \A_SPW_TOP|rx_data|always0~0_combout ;wire \A_SPW_TOP|rx_data|overflow_credit_error~q ;wire \A_SPW_TOP|SPW|FSM|Add0~30 ;wire \A_SPW_TOP|SPW|FSM|Add0~25_sumout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always8~0_combout ;wire \A_SPW_TOP|SPW|RX|always11~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct_fsm~q ;wire \A_SPW_TOP|SPW|FSM|Selector1~2_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_nchar~q ;wire \A_SPW_TOP|SPW|RX|last_was_control~q ;wire \A_SPW_TOP|SPW|RX|last_was_timec~q ;wire \A_SPW_TOP|SPW|RX|rx_error~7_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_1~q ;wire \A_SPW_TOP|SPW|RX|bit_d_3~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_3~q ;wire \A_SPW_TOP|SPW|RX|bit_d_5~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_5~q ;wire \A_SPW_TOP|SPW|RX|dta_timec[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|timecode[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|timecode[7]~0_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_0~q ;wire \A_SPW_TOP|SPW|RX|bit_d_2~q ;wire \A_SPW_TOP|SPW|RX|dta_timec[5]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[4]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec[7]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_4~q ;wire \A_SPW_TOP|SPW|RX|timecode[3]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~0_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_6~q ;wire \A_SPW_TOP|SPW|RX|bit_d_7~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_7~q ;wire \A_SPW_TOP|SPW|RX|dta_timec[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~1_combout ;wire \A_SPW_TOP|SPW|RX|bit_c_3~q ;wire \A_SPW_TOP|SPW|RX|always9~6_combout ;wire \A_SPW_TOP|SPW|RX|last_was_data~q ;wire \A_SPW_TOP|SPW|RX|rx_error~6_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~8_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~5_combout ;wire \A_SPW_TOP|SPW|RX|always9~5_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_9~feeder_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_9~q ;wire \A_SPW_TOP|SPW|RX|dta_timec[9]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data[9]~0_combout ;wire \A_SPW_TOP|SPW|RX|bit_d_8~q ;wire \A_SPW_TOP|SPW|RX|data[8]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~4_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~2_combout ;wire \A_SPW_TOP|SPW|RX|data_l_r[2]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~3_combout ;wire \A_SPW_TOP|SPW|RX|dta_timec_p[5]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|data[6]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|always9~2_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~3_combout ;wire \A_SPW_TOP|SPW|RX|always9~7_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~4_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~9_combout ;wire \A_SPW_TOP|SPW|RX|rx_error~q ;wire \A_SPW_TOP|SPW|FSM|Selector1~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_null~q ;wire \A_SPW_TOP|SPW|FSM|Selector4~2_combout ;wire \A_SPW_TOP|SPW|FSM|after128us~13_combout ;wire \A_SPW_TOP|SPW|FSM|after128us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~26 ;wire \A_SPW_TOP|SPW|FSM|Add0~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~22 ;wire \A_SPW_TOP|SPW|FSM|Add0~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~18 ;wire \A_SPW_TOP|SPW|FSM|Add0~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~14 ;wire \A_SPW_TOP|SPW|FSM|Add0~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~10 ;wire \A_SPW_TOP|SPW|FSM|Add0~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~6 ;wire \A_SPW_TOP|SPW|FSM|Add0~2 ;wire \A_SPW_TOP|SPW|FSM|Add0~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~12_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~46 ;wire \A_SPW_TOP|SPW|FSM|Add0~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~11_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~42 ;wire \A_SPW_TOP|SPW|FSM|Add0~38 ;wire \A_SPW_TOP|SPW|FSM|Add0~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~8_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~1_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~3_combout ;wire \A_SPW_TOP|SPW|FSM|always0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|src_payload~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|link_start|always0~0_combout ;wire \u0|link_start|data_out~q ;wire \u0|mm_interconnect_0|cmd_mux_009|src_payload~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|link_disable|always0~0_combout ;wire \u0|link_disable|data_out~q ;wire \A_SPW_TOP|SPW|FSM|Selector2~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~4_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector1~0_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_wait~q ;wire \A_SPW_TOP|SPW|FSM|Selector2~1_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.ready~q ;wire \A_SPW_TOP|SPW|FSM|Selector4~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~4_combout ;wire \A_SPW_TOP|SPW|FSM|always2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~5_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.connecting~q ;wire \A_SPW_TOP|SPW|FSM|Selector4~6_combout ;wire \A_SPW_TOP|SPW|FSM|Selector4~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector3~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector3~1_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.started~q ;wire \A_SPW_TOP|SPW|FSM|always2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~10_combout ;wire \A_SPW_TOP|SPW|FSM|after128us[4]~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add0~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after128us~1_combout ;wire \A_SPW_TOP|SPW|FSM|Equal0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~3_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~7_combout ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~0_combout ;wire \A_SPW_TOP|SPW|FSM|got_bit_internal~q ;wire \A_SPW_TOP|SPW|FSM|Add2~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~2 ;wire \A_SPW_TOP|SPW|FSM|Add2~46 ;wire \A_SPW_TOP|SPW|FSM|Add2~41_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~10_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~42 ;wire \A_SPW_TOP|SPW|FSM|Add2~9_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~10 ;wire \A_SPW_TOP|SPW|FSM|Add2~37_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~9_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~38 ;wire \A_SPW_TOP|SPW|FSM|Add2~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~6 ;wire \A_SPW_TOP|SPW|FSM|Add2~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~8_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~45_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~11_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|FSM|LessThan2~2_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~34 ;wire \A_SPW_TOP|SPW|FSM|Add2~29_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~7_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~30 ;wire \A_SPW_TOP|SPW|FSM|Add2~25_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~6_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~26 ;wire \A_SPW_TOP|SPW|FSM|Add2~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~5_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~22 ;wire \A_SPW_TOP|SPW|FSM|Add2~17_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~4_combout ;wire \A_SPW_TOP|SPW|FSM|Add2~18 ;wire \A_SPW_TOP|SPW|FSM|Add2~13_sumout ;wire \A_SPW_TOP|SPW|FSM|after850ns~3_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~0_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~1_combout ;wire \A_SPW_TOP|SPW|FSM|Equal1~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~4_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~6_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~5_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~2_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.error_reset~q ;wire \A_SPW_TOP|SPW|FSM|after64us[0]~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~21_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~7_combout ;wire \A_SPW_TOP|SPW|FSM|Equal2~0_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~33_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~10_combout ;wire \A_SPW_TOP|SPW|FSM|after64us[0]~1_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~5_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~3_combout ;wire \A_SPW_TOP|SPW|FSM|Add1~1_sumout ;wire \A_SPW_TOP|SPW|FSM|after64us~2_combout ;wire \A_SPW_TOP|SPW|FSM|Selector0~1_combout ;wire \A_SPW_TOP|SPW|FSM|rx_resetn~q ;wire \A_SPW_TOP|SPW|RX|WideOr7~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~2_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~3_combout ;wire \A_SPW_TOP|SPW|RX|Selector1~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|RX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector3~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|RX|Selector4~1_combout ;wire \A_SPW_TOP|SPW|RX|always2~0_combout ;wire \A_SPW_TOP|SPW|RX|control_r[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|control_p_r[0]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|last_is_timec~0_combout ;wire \A_SPW_TOP|SPW|RX|last_is_timec~q ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_time_code~q ;wire \A_SPW_TOP|SPW|FSM|always0~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector5~0_combout ;wire \A_SPW_TOP|SPW|FSM|Selector5~1_combout ;wire \A_SPW_TOP|SPW|FSM|Selector5~2_combout ;wire \A_SPW_TOP|SPW|FSM|state_fsm.run~q ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|send_fct_tx~q ;wire \A_SPW_TOP|SPW|TX|first_time~feeder_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~0_combout ;wire \A_SPW_TOP|SPW|FSM|enable_tx~q ;wire \A_SPW_TOP|SPW|FSM|WideOr0~combout ;wire \A_SPW_TOP|SPW|FSM|send_null_tx~q ;wire \A_SPW_TOP|SPW|TX|Selector0~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_start~q ;wire \A_SPW_TOP|SPW|TX|Selector1~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null~q ;wire \A_SPW_TOP|SPW|TX|Add4~1_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~5_combout ;wire \u0|mm_interconnect_0|cmd_mux_015|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|timecode_tx_enable|always0~0_combout ;wire \u0|timecode_tx_enable|data_out~q ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~5_combout ;wire \A_SPW_TOP|SPW|TX|enable_time_code~0_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~6_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~3_combout ;wire \A_SPW_TOP|SPW|RX|always8~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_got_fct~q ;wire \u0|mm_interconnect_0|cmd_mux_011|src_payload~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|write_en_tx|always0~0_combout ;wire \u0|write_en_tx|data_out~q ;wire \A_SPW_TOP|tx_data|block_write~0_combout ;wire \A_SPW_TOP|tx_data|block_write~q ;wire \A_SPW_TOP|tx_data|Add1~21_sumout ;wire \A_SPW_TOP|tx_data|counter[0]~feeder_combout ;wire \A_SPW_TOP|tx_data|f_empty~q ;wire \A_SPW_TOP|tx_data|block_read~0_combout ;wire \A_SPW_TOP|tx_data|block_read~q ;wire \A_SPW_TOP|tx_data|counter[5]~0_combout ;wire \A_SPW_TOP|tx_data|Add1~22 ;wire \A_SPW_TOP|tx_data|Add1~17_sumout ;wire \A_SPW_TOP|tx_data|counter[1]~feeder_combout ;wire \A_SPW_TOP|tx_data|Add1~18 ;wire \A_SPW_TOP|tx_data|Add1~14 ;wire \A_SPW_TOP|tx_data|Add1~9_sumout ;wire \A_SPW_TOP|tx_data|Add1~10 ;wire \A_SPW_TOP|tx_data|Add1~5_sumout ;wire \A_SPW_TOP|tx_data|counter[4]~feeder_combout ;wire \A_SPW_TOP|tx_data|Add1~6 ;wire \A_SPW_TOP|tx_data|Add1~1_sumout ;wire \A_SPW_TOP|tx_data|Equal0~0_combout ;wire \A_SPW_TOP|tx_data|f_full~q ;wire \A_SPW_TOP|tx_data|always1~1_combout ;wire \A_SPW_TOP|tx_data|Add1~13_sumout ;wire \A_SPW_TOP|tx_data|Equal1~0_combout ;wire \A_SPW_TOP|tx_data|write_tx~0_combout ;wire \A_SPW_TOP|tx_data|write_tx~q ;wire \A_SPW_TOP|SPW|TX|always7~4_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~1_combout ;wire \A_SPW_TOP|SPW|TX|block_sum~0_combout ;wire \A_SPW_TOP|SPW|TX|block_sum~q ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~8_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~12_combout ;wire \A_SPW_TOP|SPW|TX|enable_n_char~2_combout ;wire \A_SPW_TOP|SPW|TX|enable_n_char~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[0]~6_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~7_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[1]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~4_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~5_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~10_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~11_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~3_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~9_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive[5]~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~0_combout ;wire \A_SPW_TOP|SPW|TX|fct_counter_receive~2_combout ;wire \A_SPW_TOP|SPW|TX|LessThan2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector2~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector2~1_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_null_fct~q ;wire \A_SPW_TOP|SPW|TX|Selector5~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[0]~4_combout ;wire \A_SPW_TOP|tx_data|Add0~21_sumout ;wire \A_SPW_TOP|tx_data|Add0~22 ;wire \A_SPW_TOP|tx_data|Add0~13_sumout ;wire \A_SPW_TOP|tx_data|Add0~14 ;wire \A_SPW_TOP|tx_data|Add0~9_sumout ;wire \A_SPW_TOP|tx_data|Add0~10 ;wire \A_SPW_TOP|tx_data|Add0~5_sumout ;wire \A_SPW_TOP|tx_data|Add0~6 ;wire \A_SPW_TOP|tx_data|Add0~1_sumout ;wire \A_SPW_TOP|tx_data|Decoder0~21_combout ;wire \A_SPW_TOP|tx_data|Add0~2 ;wire \A_SPW_TOP|tx_data|Add0~17_sumout ;wire \A_SPW_TOP|tx_data|Decoder0~23_combout ;wire \A_SPW_TOP|tx_data|mem[56][8]~q ;wire \A_SPW_TOP|tx_data|rd_ptr[0]~0_combout ;wire \A_SPW_TOP|tx_data|rd_ptr[0]~feeder_combout ;wire \A_SPW_TOP|tx_data|always1~0_combout ;wire \A_SPW_TOP|tx_data|Add3~4_combout ;wire \A_SPW_TOP|tx_data|rd_ptr[1]~feeder_combout ;wire \A_SPW_TOP|tx_data|Add3~1_combout ;wire \A_SPW_TOP|tx_data|mem[24][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~22_combout ;wire \A_SPW_TOP|tx_data|mem[24][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~24_combout ;wire \A_SPW_TOP|tx_data|Decoder0~25_combout ;wire \A_SPW_TOP|tx_data|mem[28][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~26_combout ;wire \A_SPW_TOP|tx_data|mem[60][8]~q ;wire \A_SPW_TOP|tx_data|Add3~2_combout ;wire \A_SPW_TOP|tx_data|Add3~3_combout ;wire \A_SPW_TOP|tx_data|rd_ptr[4]~feeder_combout ;wire \A_SPW_TOP|tx_data|Add3~0_combout ;wire \A_SPW_TOP|tx_data|rd_ptr[5]~feeder_combout ;wire \A_SPW_TOP|tx_data|Mux0~3_combout ;wire \A_SPW_TOP|tx_data|mem[12][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~12_combout ;wire \A_SPW_TOP|tx_data|Decoder0~13_combout ;wire \A_SPW_TOP|tx_data|mem[12][8]~q ;wire \A_SPW_TOP|tx_data|mem[40][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~10_combout ;wire \A_SPW_TOP|tx_data|Decoder0~0_combout ;wire \A_SPW_TOP|tx_data|Decoder0~11_combout ;wire \A_SPW_TOP|tx_data|mem[40][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~8_combout ;wire \A_SPW_TOP|tx_data|Decoder0~9_combout ;wire \A_SPW_TOP|tx_data|mem[8][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~5_combout ;wire \A_SPW_TOP|tx_data|Decoder0~14_combout ;wire \A_SPW_TOP|tx_data|mem[44][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~1_combout ;wire \A_SPW_TOP|tx_data|Decoder0~1_combout ;wire \A_SPW_TOP|tx_data|Decoder0~6_combout ;wire \A_SPW_TOP|tx_data|mem[4][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~3_combout ;wire \A_SPW_TOP|tx_data|Decoder0~4_combout ;wire \A_SPW_TOP|tx_data|mem[32][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~2_combout ;wire \A_SPW_TOP|tx_data|mem[0][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~7_combout ;wire \A_SPW_TOP|tx_data|mem[36][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~0_combout ;wire \A_SPW_TOP|tx_data|Decoder0~18_combout ;wire \A_SPW_TOP|tx_data|Decoder0~19_combout ;wire \A_SPW_TOP|tx_data|mem[20][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~15_combout ;wire \A_SPW_TOP|tx_data|Decoder0~17_combout ;wire \A_SPW_TOP|tx_data|mem[48][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~20_combout ;wire \A_SPW_TOP|tx_data|mem[52][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~16_combout ;wire \A_SPW_TOP|tx_data|mem[16][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~2_combout ;wire \A_SPW_TOP|tx_data|Mux0~4_combout ;wire \A_SPW_TOP|tx_data|Decoder0~56_combout ;wire \A_SPW_TOP|tx_data|mem[13][8]~q ;wire \A_SPW_TOP|tx_data|mem[9][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~54_combout ;wire \A_SPW_TOP|tx_data|mem[9][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~57_combout ;wire \A_SPW_TOP|tx_data|mem[45][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~55_combout ;wire \A_SPW_TOP|tx_data|mem[41][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~11_combout ;wire \A_SPW_TOP|tx_data|Decoder0~59_combout ;wire \A_SPW_TOP|tx_data|mem[49][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~58_combout ;wire \A_SPW_TOP|tx_data|mem[17][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~61_combout ;wire \A_SPW_TOP|tx_data|mem[53][8]~q ;wire \A_SPW_TOP|tx_data|mem[21][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~60_combout ;wire \A_SPW_TOP|tx_data|mem[21][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~12_combout ;wire \A_SPW_TOP|tx_data|Decoder0~50_combout ;wire \A_SPW_TOP|tx_data|Decoder0~51_combout ;wire \A_SPW_TOP|tx_data|mem[33][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~48_combout ;wire \A_SPW_TOP|tx_data|Decoder0~49_combout ;wire \A_SPW_TOP|tx_data|mem[1][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~53_combout ;wire \A_SPW_TOP|tx_data|mem[37][8]~q ;wire \A_SPW_TOP|tx_data|mem[5][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~52_combout ;wire \A_SPW_TOP|tx_data|mem[5][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~10_combout ;wire \A_SPW_TOP|tx_data|Decoder0~64_combout ;wire \A_SPW_TOP|tx_data|mem[29][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~63_combout ;wire \A_SPW_TOP|tx_data|mem[57][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~62_combout ;wire \A_SPW_TOP|tx_data|mem[25][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~65_combout ;wire \A_SPW_TOP|tx_data|mem[61][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~13_combout ;wire \A_SPW_TOP|tx_data|Mux0~14_combout ;wire \A_SPW_TOP|tx_data|Decoder0~27_combout ;wire \A_SPW_TOP|tx_data|Decoder0~32_combout ;wire \A_SPW_TOP|tx_data|mem[34][8]~q ;wire \A_SPW_TOP|tx_data|mem[42][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~33_combout ;wire \A_SPW_TOP|tx_data|mem[42][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~35_combout ;wire \A_SPW_TOP|tx_data|Decoder0~36_combout ;wire \A_SPW_TOP|tx_data|mem[58][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~34_combout ;wire \A_SPW_TOP|tx_data|mem[50][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~6_combout ;wire \A_SPW_TOP|tx_data|Decoder0~37_combout ;wire \A_SPW_TOP|tx_data|Decoder0~44_combout ;wire \A_SPW_TOP|tx_data|mem[38][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~45_combout ;wire \A_SPW_TOP|tx_data|mem[46][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~46_combout ;wire \A_SPW_TOP|tx_data|mem[54][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~42_combout ;wire \A_SPW_TOP|tx_data|Decoder0~47_combout ;wire \A_SPW_TOP|tx_data|mem[62][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~8_combout ;wire \A_SPW_TOP|tx_data|Decoder0~30_combout ;wire \A_SPW_TOP|tx_data|mem[18][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~29_combout ;wire \A_SPW_TOP|tx_data|mem[10][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~31_combout ;wire \A_SPW_TOP|tx_data|mem[26][8]~q ;wire \A_SPW_TOP|tx_data|mem[2][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~28_combout ;wire \A_SPW_TOP|tx_data|mem[2][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~5_combout ;wire \A_SPW_TOP|tx_data|Decoder0~40_combout ;wire \A_SPW_TOP|tx_data|Decoder0~41_combout ;wire \A_SPW_TOP|tx_data|mem[22][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~39_combout ;wire \A_SPW_TOP|tx_data|mem[14][8]~q ;wire \A_SPW_TOP|tx_data|mem[6][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~38_combout ;wire \A_SPW_TOP|tx_data|mem[6][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~43_combout ;wire \A_SPW_TOP|tx_data|mem[30][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~7_combout ;wire \A_SPW_TOP|tx_data|Mux0~9_combout ;wire \A_SPW_TOP|tx_data|Decoder0~70_combout ;wire \A_SPW_TOP|tx_data|mem[35][8]~q ;wire \A_SPW_TOP|tx_data|mem[51][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~72_combout ;wire \A_SPW_TOP|tx_data|mem[51][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~71_combout ;wire \A_SPW_TOP|tx_data|mem[43][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~73_combout ;wire \A_SPW_TOP|tx_data|mem[59][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~16_combout ;wire \A_SPW_TOP|tx_data|mem[39][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~78_combout ;wire \A_SPW_TOP|tx_data|mem[39][8]~q ;wire \A_SPW_TOP|tx_data|mem[55][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~80_combout ;wire \A_SPW_TOP|tx_data|mem[55][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~81_combout ;wire \A_SPW_TOP|tx_data|mem[63][8]~q ;wire \A_SPW_TOP|tx_data|mem[47][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~79_combout ;wire \A_SPW_TOP|tx_data|mem[47][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~18_combout ;wire \A_SPW_TOP|tx_data|Decoder0~67_combout ;wire \A_SPW_TOP|tx_data|mem[11][8]~q ;wire \A_SPW_TOP|tx_data|mem[3][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~66_combout ;wire \A_SPW_TOP|tx_data|mem[3][8]~q ;wire \A_SPW_TOP|tx_data|mem[19][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~68_combout ;wire \A_SPW_TOP|tx_data|mem[19][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~69_combout ;wire \A_SPW_TOP|tx_data|mem[27][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~15_combout ;wire \A_SPW_TOP|tx_data|mem[7][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~74_combout ;wire \A_SPW_TOP|tx_data|mem[7][8]~q ;wire \A_SPW_TOP|tx_data|mem[15][8]~feeder_combout ;wire \A_SPW_TOP|tx_data|Decoder0~75_combout ;wire \A_SPW_TOP|tx_data|mem[15][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~77_combout ;wire \A_SPW_TOP|tx_data|mem[31][8]~q ;wire \A_SPW_TOP|tx_data|Decoder0~76_combout ;wire \A_SPW_TOP|tx_data|mem[23][8]~q ;wire \A_SPW_TOP|tx_data|Mux0~17_combout ;wire \A_SPW_TOP|tx_data|Mux0~19_combout ;wire \A_SPW_TOP|tx_data|Mux0~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type~10_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_data~q ;wire \A_SPW_TOP|SPW|TX|Selector4~4_combout ;wire \A_SPW_TOP|SPW|TX|hold_fct~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_fct~q ;wire \A_SPW_TOP|SPW|TX|always7~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector5~1_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~3_combout ;wire \A_SPW_TOP|SPW|TX|last_type~11_combout ;wire \A_SPW_TOP|SPW|TX|enable_n_char~0_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~0_combout ;wire \A_SPW_TOP|SPW|TX|Equal4~2_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~1_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~2_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~q ;wire \A_SPW_TOP|SPW|TX|always7~2_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~0_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~2_combout ;wire \A_SPW_TOP|SPW|TX|first_time~q ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~0_combout ;wire \A_SPW_TOP|SPW|TX|Add4~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~3_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[0]~1_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[0]~2_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~7_combout ;wire \A_SPW_TOP|SPW|TX|Equal4~4_combout ;wire \A_SPW_TOP|SPW|TX|Add2~0_combout ;wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~0_combout ;wire \A_SPW_TOP|rx_data|open_slot_fct~q ;wire \A_SPW_TOP|SPW|TX|hold_fct~1_combout ;wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~1_combout ;wire \A_SPW_TOP|SPW|TX|block_sum_fct_send~q ;wire \A_SPW_TOP|SPW|TX|fct_flag[1]~0_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag[1]~2_combout ;wire \A_SPW_TOP|SPW|TX|always7~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~5_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~0_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~6_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~8_combout ;wire \A_SPW_TOP|SPW|TX|always7~5_combout ;wire \A_SPW_TOP|SPW|TX|Selector3~0_combout ;wire \A_SPW_TOP|SPW|TX|state_tx.tx_spw_full~q ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[0]~0_combout ;wire \A_SPW_TOP|SPW|TX|Add4~2_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer~6_combout ;wire \A_SPW_TOP|SPW|TX|Equal4~3_combout ;wire \A_SPW_TOP|SPW|TX|hold_null~0_combout ;wire \A_SPW_TOP|SPW|TX|hold_null~q ;wire \A_SPW_TOP|SPW|TX|always7~3_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~5_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag[1]~3_combout ;wire \A_SPW_TOP|SPW|TX|Add2~1_combout ;wire \A_SPW_TOP|SPW|TX|fct_flag~4_combout ;wire \A_SPW_TOP|SPW|TX|Selector4~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~9_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|waitrequest_reset_override~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter[0]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|write_data_fifo_tx|always0~0_combout ;wire \A_SPW_TOP|tx_data|mem[56][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[56][1]~q ;wire \A_SPW_TOP|tx_data|mem[57][1]~q ;wire \A_SPW_TOP|tx_data|mem[58][1]~q ;wire \A_SPW_TOP|tx_data|mem[59][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~8_combout ;wire \A_SPW_TOP|tx_data|mem[50][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[50][1]~q ;wire \A_SPW_TOP|tx_data|mem[49][1]~q ;wire \A_SPW_TOP|tx_data|mem[51][1]~q ;wire \A_SPW_TOP|tx_data|mem[48][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~7_combout ;wire \A_SPW_TOP|tx_data|mem[18][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[18][1]~q ;wire \A_SPW_TOP|tx_data|mem[17][1]~q ;wire \A_SPW_TOP|tx_data|mem[16][1]~q ;wire \A_SPW_TOP|tx_data|mem[19][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~5_combout ;wire \A_SPW_TOP|tx_data|mem[25][1]~q ;wire \A_SPW_TOP|tx_data|mem[26][1]~q ;wire \A_SPW_TOP|tx_data|mem[27][1]~q ;wire \A_SPW_TOP|tx_data|mem[24][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[24][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~6_combout ;wire \A_SPW_TOP|tx_data|Mux7~9_combout ;wire \A_SPW_TOP|tx_data|mem[36][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[36][1]~q ;wire \A_SPW_TOP|tx_data|mem[37][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[37][1]~q ;wire \A_SPW_TOP|tx_data|mem[39][1]~q ;wire \A_SPW_TOP|tx_data|mem[38][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~12_combout ;wire \A_SPW_TOP|tx_data|mem[6][1]~q ;wire \A_SPW_TOP|tx_data|mem[4][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[4][1]~q ;wire \A_SPW_TOP|tx_data|mem[7][1]~q ;wire \A_SPW_TOP|tx_data|mem[5][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[5][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~10_combout ;wire \A_SPW_TOP|tx_data|mem[14][1]~q ;wire \A_SPW_TOP|tx_data|mem[13][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[13][1]~q ;wire \A_SPW_TOP|tx_data|mem[15][1]~q ;wire \A_SPW_TOP|tx_data|mem[12][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[12][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~11_combout ;wire \A_SPW_TOP|tx_data|mem[46][1]~q ;wire \A_SPW_TOP|tx_data|mem[45][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[45][1]~q ;wire \A_SPW_TOP|tx_data|mem[47][1]~q ;wire \A_SPW_TOP|tx_data|mem[44][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[44][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~13_combout ;wire \A_SPW_TOP|tx_data|Mux7~14_combout ;wire \A_SPW_TOP|tx_data|mem[22][1]~q ;wire \A_SPW_TOP|tx_data|mem[52][1]~q ;wire \A_SPW_TOP|tx_data|mem[20][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[20][1]~q ;wire \A_SPW_TOP|tx_data|mem[54][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~15_combout ;wire \A_SPW_TOP|tx_data|mem[60][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[60][1]~q ;wire \A_SPW_TOP|tx_data|mem[28][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[28][1]~q ;wire \A_SPW_TOP|tx_data|mem[62][1]~q ;wire \A_SPW_TOP|tx_data|mem[30][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~16_combout ;wire \A_SPW_TOP|tx_data|mem[61][1]~q ;wire \A_SPW_TOP|tx_data|mem[29][1]~q ;wire \A_SPW_TOP|tx_data|mem[31][1]~q ;wire \A_SPW_TOP|tx_data|mem[63][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~18_combout ;wire \A_SPW_TOP|tx_data|mem[53][1]~q ;wire \A_SPW_TOP|tx_data|mem[23][1]~q ;wire \A_SPW_TOP|tx_data|mem[55][1]~q ;wire \A_SPW_TOP|tx_data|mem[21][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~17_combout ;wire \A_SPW_TOP|tx_data|Mux7~19_combout ;wire \A_SPW_TOP|tx_data|mem[1][1]~q ;wire \A_SPW_TOP|tx_data|mem[2][1]~q ;wire \A_SPW_TOP|tx_data|mem[3][1]~q ;wire \A_SPW_TOP|tx_data|mem[0][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~0_combout ;wire \A_SPW_TOP|tx_data|mem[42][1]~q ;wire \A_SPW_TOP|tx_data|mem[40][1]~q ;wire \A_SPW_TOP|tx_data|mem[43][1]~q ;wire \A_SPW_TOP|tx_data|mem[41][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~3_combout ;wire \A_SPW_TOP|tx_data|mem[10][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[10][1]~q ;wire \A_SPW_TOP|tx_data|mem[9][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[9][1]~q ;wire \A_SPW_TOP|tx_data|mem[11][1]~q ;wire \A_SPW_TOP|tx_data|mem[8][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~1_combout ;wire \A_SPW_TOP|tx_data|mem[32][1]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[32][1]~q ;wire \A_SPW_TOP|tx_data|mem[35][1]~q ;wire \A_SPW_TOP|tx_data|mem[34][1]~q ;wire \A_SPW_TOP|tx_data|mem[33][1]~q ;wire \A_SPW_TOP|tx_data|Mux7~2_combout ;wire \A_SPW_TOP|tx_data|Mux7~4_combout ;wire \A_SPW_TOP|tx_data|Mux7~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type~13_combout ;wire \A_SPW_TOP|SPW|TX|last_type~12_combout ;wire \A_SPW_TOP|SPW|TX|last_type~14_combout ;wire \A_SPW_TOP|SPW|TX|last_type.TIMEC~q ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~0_combout ;wire \A_SPW_TOP|tx_data|mem[6][0]~q ;wire \A_SPW_TOP|tx_data|mem[2][0]~q ;wire \A_SPW_TOP|tx_data|mem[22][0]~q ;wire \A_SPW_TOP|tx_data|mem[18][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~2_combout ;wire \A_SPW_TOP|tx_data|mem[1][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[1][0]~q ;wire \A_SPW_TOP|tx_data|mem[17][0]~q ;wire \A_SPW_TOP|tx_data|mem[21][0]~q ;wire \A_SPW_TOP|tx_data|mem[5][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~1_combout ;wire \A_SPW_TOP|tx_data|mem[7][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[7][0]~q ;wire \A_SPW_TOP|tx_data|mem[3][0]~q ;wire \A_SPW_TOP|tx_data|mem[23][0]~q ;wire \A_SPW_TOP|tx_data|mem[19][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[19][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~3_combout ;wire \A_SPW_TOP|tx_data|mem[0][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][0]~q ;wire \A_SPW_TOP|tx_data|mem[4][0]~q ;wire \A_SPW_TOP|tx_data|mem[20][0]~q ;wire \A_SPW_TOP|tx_data|mem[16][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~0_combout ;wire \A_SPW_TOP|tx_data|Mux8~4_combout ;wire \A_SPW_TOP|tx_data|mem[42][0]~q ;wire \A_SPW_TOP|tx_data|mem[40][0]~q ;wire \A_SPW_TOP|tx_data|mem[58][0]~q ;wire \A_SPW_TOP|tx_data|mem[56][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~15_combout ;wire \A_SPW_TOP|tx_data|mem[44][0]~q ;wire \A_SPW_TOP|tx_data|mem[60][0]~q ;wire \A_SPW_TOP|tx_data|mem[62][0]~q ;wire \A_SPW_TOP|tx_data|mem[46][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~17_combout ;wire \A_SPW_TOP|tx_data|mem[57][0]~q ;wire \A_SPW_TOP|tx_data|mem[41][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[41][0]~q ;wire \A_SPW_TOP|tx_data|mem[59][0]~q ;wire \A_SPW_TOP|tx_data|mem[43][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~16_combout ;wire \A_SPW_TOP|tx_data|mem[45][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[45][0]~q ;wire \A_SPW_TOP|tx_data|mem[47][0]~q ;wire \A_SPW_TOP|tx_data|mem[63][0]~q ;wire \A_SPW_TOP|tx_data|mem[61][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~18_combout ;wire \A_SPW_TOP|tx_data|Mux8~19_combout ;wire \A_SPW_TOP|tx_data|mem[27][0]~q ;wire \A_SPW_TOP|tx_data|mem[31][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[31][0]~q ;wire \A_SPW_TOP|tx_data|mem[26][0]~q ;wire \A_SPW_TOP|tx_data|mem[30][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~8_combout ;wire \A_SPW_TOP|tx_data|mem[10][0]~q ;wire \A_SPW_TOP|tx_data|mem[11][0]~q ;wire \A_SPW_TOP|tx_data|mem[15][0]~q ;wire \A_SPW_TOP|tx_data|mem[14][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~7_combout ;wire \A_SPW_TOP|tx_data|mem[24][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[24][0]~q ;wire \A_SPW_TOP|tx_data|mem[25][0]~q ;wire \A_SPW_TOP|tx_data|mem[29][0]~q ;wire \A_SPW_TOP|tx_data|mem[28][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~6_combout ;wire \A_SPW_TOP|tx_data|mem[12][0]~q ;wire \A_SPW_TOP|tx_data|mem[9][0]~q ;wire \A_SPW_TOP|tx_data|mem[13][0]~q ;wire \A_SPW_TOP|tx_data|mem[8][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~5_combout ;wire \A_SPW_TOP|tx_data|Mux8~9_combout ;wire \A_SPW_TOP|tx_data|mem[35][0]~q ;wire \A_SPW_TOP|tx_data|mem[39][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[39][0]~q ;wire \A_SPW_TOP|tx_data|mem[55][0]~q ;wire \A_SPW_TOP|tx_data|mem[51][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~13_combout ;wire \A_SPW_TOP|tx_data|mem[32][0]~q ;wire \A_SPW_TOP|tx_data|mem[48][0]~q ;wire \A_SPW_TOP|tx_data|mem[52][0]~q ;wire \A_SPW_TOP|tx_data|mem[36][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~10_combout ;wire \A_SPW_TOP|tx_data|mem[33][0]~q ;wire \A_SPW_TOP|tx_data|mem[37][0]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[37][0]~q ;wire \A_SPW_TOP|tx_data|mem[53][0]~q ;wire \A_SPW_TOP|tx_data|mem[49][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~11_combout ;wire \A_SPW_TOP|tx_data|mem[38][0]~q ;wire \A_SPW_TOP|tx_data|mem[50][0]~q ;wire \A_SPW_TOP|tx_data|mem[54][0]~q ;wire \A_SPW_TOP|tx_data|mem[34][0]~q ;wire \A_SPW_TOP|tx_data|Mux8~12_combout ;wire \A_SPW_TOP|tx_data|Mux8~14_combout ;wire \A_SPW_TOP|tx_data|Mux8~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type~23_combout ;wire \A_SPW_TOP|SPW|TX|last_type~24_combout ;wire \A_SPW_TOP|SPW|TX|last_type.NULL~q ;wire \A_SPW_TOP|SPW|TX|Equal4~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~19_combout ;wire \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx~1_combout ;wire \A_SPW_TOP|SPW|TX|last_type~20_combout ;wire \A_SPW_TOP|SPW|TX|Equal14~0_combout ;wire \A_SPW_TOP|SPW|TX|LessThan1~0_combout ;wire \A_SPW_TOP|SPW|TX|last_type~17_combout ;wire \A_SPW_TOP|SPW|TX|last_type~18_combout ;wire \A_SPW_TOP|SPW|TX|last_type~21_combout ;wire \A_SPW_TOP|SPW|TX|last_type.EOP~q ;wire \A_SPW_TOP|SPW|TX|last_type~22_combout ;wire \A_SPW_TOP|SPW|TX|last_type.EEP~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~10_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~20_combout ;wire \A_SPW_TOP|SPW|TX|last_type~26_combout ;wire \A_SPW_TOP|SPW|TX|last_type~27_combout ;wire \A_SPW_TOP|SPW|TX|last_type~15_combout ;wire \A_SPW_TOP|SPW|TX|last_type~16_combout ;wire \A_SPW_TOP|SPW|TX|last_type.DATA~q ;wire \A_SPW_TOP|SPW|TX|always3~1_combout ;wire \A_SPW_TOP|SPW|TX|last_type~25_combout ;wire \A_SPW_TOP|SPW|TX|last_type.FCT~q ;wire \A_SPW_TOP|SPW|TX|always3~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~2_combout ;wire \A_SPW_TOP|SPW|TX|always2~6_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3]~feeder_combout ;wire \u0|timecode_tx_data|always0~0_combout ;wire \A_SPW_TOP|SPW|TX|global_counter_transfer[0]~8_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~0_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s~0_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s[9]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~6_combout ;wire \u0|timecode_tx_data|data_out[6]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~7_combout ;wire \u0|timecode_tx_data|data_out[7]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s[7]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~3_combout ;wire \u0|timecode_tx_data|data_out[3]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~5_combout ;wire \u0|timecode_tx_data|data_out[5]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_payload~4_combout ;wire \u0|timecode_tx_data|data_out[4]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|timecode_s[4]~feeder_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_timecode~3_combout ;wire \A_SPW_TOP|SPW|TX|always2~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~5_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~6_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~5_combout ;wire \A_SPW_TOP|tx_data|mem[49][5]~q ;wire \A_SPW_TOP|tx_data|mem[37][5]~q ;wire \A_SPW_TOP|tx_data|mem[33][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[33][5]~q ;wire \A_SPW_TOP|tx_data|mem[53][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~11_combout ;wire \A_SPW_TOP|tx_data|mem[32][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[32][5]~q ;wire \A_SPW_TOP|tx_data|mem[48][5]~q ;wire \A_SPW_TOP|tx_data|mem[52][5]~q ;wire \A_SPW_TOP|tx_data|mem[36][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[36][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~10_combout ;wire \A_SPW_TOP|tx_data|mem[51][5]~q ;wire \A_SPW_TOP|tx_data|mem[35][5]~q ;wire \A_SPW_TOP|tx_data|mem[55][5]~q ;wire \A_SPW_TOP|tx_data|mem[39][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~13_combout ;wire \A_SPW_TOP|tx_data|mem[34][5]~q ;wire \A_SPW_TOP|tx_data|mem[38][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[38][5]~q ;wire \A_SPW_TOP|tx_data|mem[50][5]~q ;wire \A_SPW_TOP|tx_data|mem[54][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~12_combout ;wire \A_SPW_TOP|tx_data|Mux3~14_combout ;wire \A_SPW_TOP|tx_data|mem[3][5]~q ;wire \A_SPW_TOP|tx_data|mem[19][5]~q ;wire \A_SPW_TOP|tx_data|mem[7][5]~q ;wire \A_SPW_TOP|tx_data|mem[23][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~3_combout ;wire \A_SPW_TOP|tx_data|mem[18][5]~q ;wire \A_SPW_TOP|tx_data|mem[2][5]~q ;wire \A_SPW_TOP|tx_data|mem[22][5]~q ;wire \A_SPW_TOP|tx_data|mem[6][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~2_combout ;wire \A_SPW_TOP|tx_data|mem[4][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[4][5]~q ;wire \A_SPW_TOP|tx_data|mem[16][5]~q ;wire \A_SPW_TOP|tx_data|mem[20][5]~q ;wire \A_SPW_TOP|tx_data|mem[0][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~0_combout ;wire \A_SPW_TOP|tx_data|mem[1][5]~q ;wire \A_SPW_TOP|tx_data|mem[5][5]~q ;wire \A_SPW_TOP|tx_data|mem[17][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[17][5]~q ;wire \A_SPW_TOP|tx_data|mem[21][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[21][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~1_combout ;wire \A_SPW_TOP|tx_data|Mux3~4_combout ;wire \A_SPW_TOP|tx_data|mem[42][5]~q ;wire \A_SPW_TOP|tx_data|mem[40][5]~q ;wire \A_SPW_TOP|tx_data|mem[56][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[56][5]~q ;wire \A_SPW_TOP|tx_data|mem[58][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~15_combout ;wire \A_SPW_TOP|tx_data|mem[41][5]~q ;wire \A_SPW_TOP|tx_data|mem[57][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[57][5]~q ;wire \A_SPW_TOP|tx_data|mem[59][5]~q ;wire \A_SPW_TOP|tx_data|mem[43][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[43][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~16_combout ;wire \A_SPW_TOP|tx_data|mem[46][5]~q ;wire \A_SPW_TOP|tx_data|mem[60][5]~q ;wire \A_SPW_TOP|tx_data|mem[44][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[44][5]~q ;wire \A_SPW_TOP|tx_data|mem[62][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~17_combout ;wire \A_SPW_TOP|tx_data|mem[45][5]~q ;wire \A_SPW_TOP|tx_data|mem[47][5]~q ;wire \A_SPW_TOP|tx_data|mem[63][5]~q ;wire \A_SPW_TOP|tx_data|mem[61][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[61][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~18_combout ;wire \A_SPW_TOP|tx_data|Mux3~19_combout ;wire \A_SPW_TOP|tx_data|mem[8][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][5]~q ;wire \A_SPW_TOP|tx_data|mem[24][5]~q ;wire \A_SPW_TOP|tx_data|mem[12][5]~q ;wire \A_SPW_TOP|tx_data|mem[28][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~5_combout ;wire \A_SPW_TOP|tx_data|mem[9][5]~q ;wire \A_SPW_TOP|tx_data|mem[13][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[13][5]~q ;wire \A_SPW_TOP|tx_data|mem[29][5]~q ;wire \A_SPW_TOP|tx_data|mem[25][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~6_combout ;wire \A_SPW_TOP|tx_data|mem[15][5]~q ;wire \A_SPW_TOP|tx_data|mem[27][5]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[27][5]~q ;wire \A_SPW_TOP|tx_data|mem[31][5]~q ;wire \A_SPW_TOP|tx_data|mem[11][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~8_combout ;wire \A_SPW_TOP|tx_data|mem[10][5]~q ;wire \A_SPW_TOP|tx_data|mem[14][5]~q ;wire \A_SPW_TOP|tx_data|mem[30][5]~q ;wire \A_SPW_TOP|tx_data|mem[26][5]~q ;wire \A_SPW_TOP|tx_data|Mux3~7_combout ;wire \A_SPW_TOP|tx_data|Mux3~9_combout ;wire \A_SPW_TOP|tx_data|Mux3~20_combout ;wire \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last[7]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~2_combout ;wire \u0|write_data_fifo_tx|data_out[2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[56][2]~q ;wire \A_SPW_TOP|tx_data|mem[40][2]~q ;wire \A_SPW_TOP|tx_data|mem[58][2]~q ;wire \A_SPW_TOP|tx_data|mem[42][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~15_combout ;wire \A_SPW_TOP|tx_data|mem[57][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[57][2]~q ;wire \A_SPW_TOP|tx_data|mem[41][2]~q ;wire \A_SPW_TOP|tx_data|mem[59][2]~q ;wire \A_SPW_TOP|tx_data|mem[43][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[43][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~16_combout ;wire \A_SPW_TOP|tx_data|mem[47][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[47][2]~q ;wire \A_SPW_TOP|tx_data|mem[61][2]~q ;wire \A_SPW_TOP|tx_data|mem[63][2]~q ;wire \A_SPW_TOP|tx_data|mem[45][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[45][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~18_combout ;wire \A_SPW_TOP|tx_data|mem[60][2]~q ;wire \A_SPW_TOP|tx_data|mem[44][2]~q ;wire \A_SPW_TOP|tx_data|mem[62][2]~q ;wire \A_SPW_TOP|tx_data|mem[46][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~17_combout ;wire \A_SPW_TOP|tx_data|Mux6~19_combout ;wire \A_SPW_TOP|tx_data|mem[35][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[35][2]~q ;wire \A_SPW_TOP|tx_data|mem[39][2]~q ;wire \A_SPW_TOP|tx_data|mem[51][2]~q ;wire \A_SPW_TOP|tx_data|mem[55][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~13_combout ;wire \A_SPW_TOP|tx_data|mem[37][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[37][2]~q ;wire \A_SPW_TOP|tx_data|mem[33][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[33][2]~q ;wire \A_SPW_TOP|tx_data|mem[53][2]~q ;wire \A_SPW_TOP|tx_data|mem[49][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[49][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~11_combout ;wire \A_SPW_TOP|tx_data|mem[36][2]~q ;wire \A_SPW_TOP|tx_data|mem[32][2]~q ;wire \A_SPW_TOP|tx_data|mem[48][2]~q ;wire \A_SPW_TOP|tx_data|mem[52][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~10_combout ;wire \A_SPW_TOP|tx_data|mem[38][2]~q ;wire \A_SPW_TOP|tx_data|mem[50][2]~q ;wire \A_SPW_TOP|tx_data|mem[34][2]~q ;wire \A_SPW_TOP|tx_data|mem[54][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~12_combout ;wire \A_SPW_TOP|tx_data|Mux6~14_combout ;wire \A_SPW_TOP|tx_data|mem[24][2]~q ;wire \A_SPW_TOP|tx_data|mem[12][2]~q ;wire \A_SPW_TOP|tx_data|mem[8][2]~q ;wire \A_SPW_TOP|tx_data|mem[28][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~5_combout ;wire \A_SPW_TOP|tx_data|mem[13][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[13][2]~q ;wire \A_SPW_TOP|tx_data|mem[25][2]~q ;wire \A_SPW_TOP|tx_data|mem[29][2]~q ;wire \A_SPW_TOP|tx_data|mem[9][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~6_combout ;wire \A_SPW_TOP|tx_data|mem[27][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[27][2]~q ;wire \A_SPW_TOP|tx_data|mem[15][2]~q ;wire \A_SPW_TOP|tx_data|mem[31][2]~q ;wire \A_SPW_TOP|tx_data|mem[11][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~8_combout ;wire \A_SPW_TOP|tx_data|mem[14][2]~q ;wire \A_SPW_TOP|tx_data|mem[26][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[26][2]~q ;wire \A_SPW_TOP|tx_data|mem[30][2]~q ;wire \A_SPW_TOP|tx_data|mem[10][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~7_combout ;wire \A_SPW_TOP|tx_data|Mux6~9_combout ;wire \A_SPW_TOP|tx_data|mem[7][2]~q ;wire \A_SPW_TOP|tx_data|mem[19][2]~q ;wire \A_SPW_TOP|tx_data|mem[23][2]~q ;wire \A_SPW_TOP|tx_data|mem[3][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~3_combout ;wire \A_SPW_TOP|tx_data|mem[17][2]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[17][2]~q ;wire \A_SPW_TOP|tx_data|mem[21][2]~q ;wire \A_SPW_TOP|tx_data|mem[5][2]~q ;wire \A_SPW_TOP|tx_data|mem[1][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~1_combout ;wire \A_SPW_TOP|tx_data|mem[18][2]~q ;wire \A_SPW_TOP|tx_data|mem[6][2]~q ;wire \A_SPW_TOP|tx_data|mem[22][2]~q ;wire \A_SPW_TOP|tx_data|mem[2][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~2_combout ;wire \A_SPW_TOP|tx_data|mem[0][2]~q ;wire \A_SPW_TOP|tx_data|mem[4][2]~q ;wire \A_SPW_TOP|tx_data|mem[20][2]~q ;wire \A_SPW_TOP|tx_data|mem[16][2]~q ;wire \A_SPW_TOP|tx_data|Mux6~0_combout ;wire \A_SPW_TOP|tx_data|Mux6~4_combout ;wire \A_SPW_TOP|tx_data|Mux6~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~7_combout ;wire \u0|write_data_fifo_tx|data_out[7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[13][7]~q ;wire \A_SPW_TOP|tx_data|mem[5][7]~q ;wire \A_SPW_TOP|tx_data|mem[37][7]~q ;wire \A_SPW_TOP|tx_data|mem[45][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~6_combout ;wire \A_SPW_TOP|tx_data|mem[33][7]~q ;wire \A_SPW_TOP|tx_data|mem[1][7]~q ;wire \A_SPW_TOP|tx_data|mem[9][7]~q ;wire \A_SPW_TOP|tx_data|mem[41][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~5_combout ;wire \A_SPW_TOP|tx_data|mem[49][7]~q ;wire \A_SPW_TOP|tx_data|mem[17][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[17][7]~q ;wire \A_SPW_TOP|tx_data|mem[57][7]~q ;wire \A_SPW_TOP|tx_data|mem[25][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~7_combout ;wire \A_SPW_TOP|tx_data|mem[21][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[21][7]~q ;wire \A_SPW_TOP|tx_data|mem[53][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[53][7]~q ;wire \A_SPW_TOP|tx_data|mem[61][7]~q ;wire \A_SPW_TOP|tx_data|mem[29][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~8_combout ;wire \A_SPW_TOP|tx_data|Mux1~9_combout ;wire \A_SPW_TOP|tx_data|mem[23][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[23][7]~q ;wire \A_SPW_TOP|tx_data|mem[19][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[19][7]~q ;wire \A_SPW_TOP|tx_data|mem[27][7]~q ;wire \A_SPW_TOP|tx_data|mem[31][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~17_combout ;wire \A_SPW_TOP|tx_data|mem[3][7]~q ;wire \A_SPW_TOP|tx_data|mem[7][7]~q ;wire \A_SPW_TOP|tx_data|mem[15][7]~q ;wire \A_SPW_TOP|tx_data|mem[11][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~15_combout ;wire \A_SPW_TOP|tx_data|mem[47][7]~q ;wire \A_SPW_TOP|tx_data|mem[43][7]~q ;wire \A_SPW_TOP|tx_data|mem[39][7]~q ;wire \A_SPW_TOP|tx_data|mem[35][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~16_combout ;wire \A_SPW_TOP|tx_data|mem[63][7]~q ;wire \A_SPW_TOP|tx_data|mem[51][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[51][7]~q ;wire \A_SPW_TOP|tx_data|mem[59][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[59][7]~q ;wire \A_SPW_TOP|tx_data|mem[55][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~18_combout ;wire \A_SPW_TOP|tx_data|Mux1~19_combout ;wire \A_SPW_TOP|tx_data|mem[38][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[38][7]~q ;wire \A_SPW_TOP|tx_data|mem[6][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[6][7]~q ;wire \A_SPW_TOP|tx_data|mem[14][7]~q ;wire \A_SPW_TOP|tx_data|mem[46][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~11_combout ;wire \A_SPW_TOP|tx_data|mem[50][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[50][7]~q ;wire \A_SPW_TOP|tx_data|mem[26][7]~q ;wire \A_SPW_TOP|tx_data|mem[58][7]~q ;wire \A_SPW_TOP|tx_data|mem[18][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~12_combout ;wire \A_SPW_TOP|tx_data|mem[22][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[22][7]~q ;wire \A_SPW_TOP|tx_data|mem[54][7]~q ;wire \A_SPW_TOP|tx_data|mem[62][7]~q ;wire \A_SPW_TOP|tx_data|mem[30][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~13_combout ;wire \A_SPW_TOP|tx_data|mem[2][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[2][7]~q ;wire \A_SPW_TOP|tx_data|mem[10][7]~q ;wire \A_SPW_TOP|tx_data|mem[42][7]~q ;wire \A_SPW_TOP|tx_data|mem[34][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~10_combout ;wire \A_SPW_TOP|tx_data|Mux1~14_combout ;wire \A_SPW_TOP|tx_data|mem[16][7]~q ;wire \A_SPW_TOP|tx_data|mem[24][7]~q ;wire \A_SPW_TOP|tx_data|mem[48][7]~q ;wire \A_SPW_TOP|tx_data|mem[56][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~2_combout ;wire \A_SPW_TOP|tx_data|mem[36][7]~q ;wire \A_SPW_TOP|tx_data|mem[12][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[12][7]~q ;wire \A_SPW_TOP|tx_data|mem[4][7]~q ;wire \A_SPW_TOP|tx_data|mem[44][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[44][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~1_combout ;wire \A_SPW_TOP|tx_data|mem[0][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][7]~q ;wire \A_SPW_TOP|tx_data|mem[32][7]~q ;wire \A_SPW_TOP|tx_data|mem[40][7]~q ;wire \A_SPW_TOP|tx_data|mem[8][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~0_combout ;wire \A_SPW_TOP|tx_data|mem[20][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[20][7]~q ;wire \A_SPW_TOP|tx_data|mem[28][7]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[28][7]~q ;wire \A_SPW_TOP|tx_data|mem[60][7]~q ;wire \A_SPW_TOP|tx_data|mem[52][7]~q ;wire \A_SPW_TOP|tx_data|Mux1~3_combout ;wire \A_SPW_TOP|tx_data|Mux1~4_combout ;wire \A_SPW_TOP|tx_data|Mux1~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~6_combout ;wire \u0|write_data_fifo_tx|data_out[6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[26][6]~q ;wire \A_SPW_TOP|tx_data|mem[25][6]~q ;wire \A_SPW_TOP|tx_data|mem[27][6]~q ;wire \A_SPW_TOP|tx_data|mem[24][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[24][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~6_combout ;wire \A_SPW_TOP|tx_data|mem[50][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[50][6]~q ;wire \A_SPW_TOP|tx_data|mem[48][6]~q ;wire \A_SPW_TOP|tx_data|mem[51][6]~q ;wire \A_SPW_TOP|tx_data|mem[49][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[49][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~7_combout ;wire \A_SPW_TOP|tx_data|mem[16][6]~q ;wire \A_SPW_TOP|tx_data|mem[17][6]~q ;wire \A_SPW_TOP|tx_data|mem[18][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[18][6]~q ;wire \A_SPW_TOP|tx_data|mem[19][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~5_combout ;wire \A_SPW_TOP|tx_data|mem[56][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[56][6]~q ;wire \A_SPW_TOP|tx_data|mem[58][6]~q ;wire \A_SPW_TOP|tx_data|mem[59][6]~q ;wire \A_SPW_TOP|tx_data|mem[57][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~8_combout ;wire \A_SPW_TOP|tx_data|Mux2~9_combout ;wire \A_SPW_TOP|tx_data|mem[42][6]~q ;wire \A_SPW_TOP|tx_data|mem[40][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[40][6]~q ;wire \A_SPW_TOP|tx_data|mem[43][6]~q ;wire \A_SPW_TOP|tx_data|mem[41][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~3_combout ;wire \A_SPW_TOP|tx_data|mem[9][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[9][6]~q ;wire \A_SPW_TOP|tx_data|mem[8][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][6]~q ;wire \A_SPW_TOP|tx_data|mem[11][6]~q ;wire \A_SPW_TOP|tx_data|mem[10][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~1_combout ;wire \A_SPW_TOP|tx_data|mem[34][6]~q ;wire \A_SPW_TOP|tx_data|mem[32][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[32][6]~q ;wire \A_SPW_TOP|tx_data|mem[35][6]~q ;wire \A_SPW_TOP|tx_data|mem[33][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[33][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~2_combout ;wire \A_SPW_TOP|tx_data|mem[2][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[2][6]~q ;wire \A_SPW_TOP|tx_data|mem[0][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][6]~q ;wire \A_SPW_TOP|tx_data|mem[1][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[1][6]~q ;wire \A_SPW_TOP|tx_data|mem[3][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~0_combout ;wire \A_SPW_TOP|tx_data|Mux2~4_combout ;wire \A_SPW_TOP|tx_data|mem[28][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[28][6]~q ;wire \A_SPW_TOP|tx_data|mem[60][6]~q ;wire \A_SPW_TOP|tx_data|mem[61][6]~q ;wire \A_SPW_TOP|tx_data|mem[29][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~16_combout ;wire \A_SPW_TOP|tx_data|mem[30][6]~q ;wire \A_SPW_TOP|tx_data|mem[62][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[62][6]~q ;wire \A_SPW_TOP|tx_data|mem[63][6]~q ;wire \A_SPW_TOP|tx_data|mem[31][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~18_combout ;wire \A_SPW_TOP|tx_data|mem[23][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[23][6]~q ;wire \A_SPW_TOP|tx_data|mem[22][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[22][6]~q ;wire \A_SPW_TOP|tx_data|mem[54][6]~q ;wire \A_SPW_TOP|tx_data|mem[55][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~17_combout ;wire \A_SPW_TOP|tx_data|mem[20][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[20][6]~q ;wire \A_SPW_TOP|tx_data|mem[52][6]~q ;wire \A_SPW_TOP|tx_data|mem[53][6]~q ;wire \A_SPW_TOP|tx_data|mem[21][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[21][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~15_combout ;wire \A_SPW_TOP|tx_data|Mux2~19_combout ;wire \A_SPW_TOP|tx_data|mem[37][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[37][6]~q ;wire \A_SPW_TOP|tx_data|mem[36][6]~q ;wire \A_SPW_TOP|tx_data|mem[39][6]~q ;wire \A_SPW_TOP|tx_data|mem[38][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~12_combout ;wire \A_SPW_TOP|tx_data|mem[5][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[5][6]~q ;wire \A_SPW_TOP|tx_data|mem[6][6]~q ;wire \A_SPW_TOP|tx_data|mem[7][6]~q ;wire \A_SPW_TOP|tx_data|mem[4][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[4][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~10_combout ;wire \A_SPW_TOP|tx_data|mem[46][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[46][6]~q ;wire \A_SPW_TOP|tx_data|mem[45][6]~q ;wire \A_SPW_TOP|tx_data|mem[47][6]~q ;wire \A_SPW_TOP|tx_data|mem[44][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[44][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~13_combout ;wire \A_SPW_TOP|tx_data|mem[14][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[14][6]~q ;wire \A_SPW_TOP|tx_data|mem[13][6]~q ;wire \A_SPW_TOP|tx_data|mem[15][6]~q ;wire \A_SPW_TOP|tx_data|mem[12][6]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[12][6]~q ;wire \A_SPW_TOP|tx_data|Mux2~11_combout ;wire \A_SPW_TOP|tx_data|Mux2~14_combout ;wire \A_SPW_TOP|tx_data|Mux2~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~4_combout ;wire \u0|write_data_fifo_tx|data_out[4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[14][4]~q ;wire \A_SPW_TOP|tx_data|mem[38][4]~q ;wire \A_SPW_TOP|tx_data|mem[46][4]~q ;wire \A_SPW_TOP|tx_data|mem[6][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~11_combout ;wire \A_SPW_TOP|tx_data|mem[18][4]~q ;wire \A_SPW_TOP|tx_data|mem[50][4]~q ;wire \A_SPW_TOP|tx_data|mem[26][4]~q ;wire \A_SPW_TOP|tx_data|mem[58][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~12_combout ;wire \A_SPW_TOP|tx_data|mem[10][4]~q ;wire \A_SPW_TOP|tx_data|mem[34][4]~q ;wire \A_SPW_TOP|tx_data|mem[42][4]~q ;wire \A_SPW_TOP|tx_data|mem[2][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[2][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~10_combout ;wire \A_SPW_TOP|tx_data|mem[22][4]~q ;wire \A_SPW_TOP|tx_data|mem[54][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[54][4]~q ;wire \A_SPW_TOP|tx_data|mem[62][4]~q ;wire \A_SPW_TOP|tx_data|mem[30][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~13_combout ;wire \A_SPW_TOP|tx_data|Mux4~14_combout ;wire \A_SPW_TOP|tx_data|mem[33][4]~q ;wire \A_SPW_TOP|tx_data|mem[1][4]~q ;wire \A_SPW_TOP|tx_data|mem[9][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[9][4]~q ;wire \A_SPW_TOP|tx_data|mem[41][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~5_combout ;wire \A_SPW_TOP|tx_data|mem[29][4]~q ;wire \A_SPW_TOP|tx_data|mem[53][4]~q ;wire \A_SPW_TOP|tx_data|mem[21][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[21][4]~q ;wire \A_SPW_TOP|tx_data|mem[61][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~8_combout ;wire \A_SPW_TOP|tx_data|mem[37][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[37][4]~q ;wire \A_SPW_TOP|tx_data|mem[13][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[13][4]~q ;wire \A_SPW_TOP|tx_data|mem[45][4]~q ;wire \A_SPW_TOP|tx_data|mem[5][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[5][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~6_combout ;wire \A_SPW_TOP|tx_data|mem[25][4]~q ;wire \A_SPW_TOP|tx_data|mem[49][4]~q ;wire \A_SPW_TOP|tx_data|mem[57][4]~q ;wire \A_SPW_TOP|tx_data|mem[17][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[17][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~7_combout ;wire \A_SPW_TOP|tx_data|Mux4~9_combout ;wire \A_SPW_TOP|tx_data|mem[15][4]~q ;wire \A_SPW_TOP|tx_data|mem[3][4]~q ;wire \A_SPW_TOP|tx_data|mem[11][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[11][4]~q ;wire \A_SPW_TOP|tx_data|mem[7][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~15_combout ;wire \A_SPW_TOP|tx_data|mem[51][4]~q ;wire \A_SPW_TOP|tx_data|mem[59][4]~q ;wire \A_SPW_TOP|tx_data|mem[63][4]~q ;wire \A_SPW_TOP|tx_data|mem[55][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~18_combout ;wire \A_SPW_TOP|tx_data|mem[39][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[39][4]~q ;wire \A_SPW_TOP|tx_data|mem[43][4]~q ;wire \A_SPW_TOP|tx_data|mem[47][4]~q ;wire \A_SPW_TOP|tx_data|mem[35][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[35][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~16_combout ;wire \A_SPW_TOP|tx_data|mem[27][4]~q ;wire \A_SPW_TOP|tx_data|mem[23][4]~q ;wire \A_SPW_TOP|tx_data|mem[31][4]~q ;wire \A_SPW_TOP|tx_data|mem[19][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~17_combout ;wire \A_SPW_TOP|tx_data|Mux4~19_combout ;wire \A_SPW_TOP|tx_data|mem[28][4]~q ;wire \A_SPW_TOP|tx_data|mem[20][4]~q ;wire \A_SPW_TOP|tx_data|mem[60][4]~q ;wire \A_SPW_TOP|tx_data|mem[52][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~3_combout ;wire \A_SPW_TOP|tx_data|mem[24][4]~q ;wire \A_SPW_TOP|tx_data|mem[16][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[16][4]~q ;wire \A_SPW_TOP|tx_data|mem[48][4]~q ;wire \A_SPW_TOP|tx_data|mem[56][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~2_combout ;wire \A_SPW_TOP|tx_data|mem[32][4]~q ;wire \A_SPW_TOP|tx_data|mem[8][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][4]~q ;wire \A_SPW_TOP|tx_data|mem[40][4]~q ;wire \A_SPW_TOP|tx_data|mem[0][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~0_combout ;wire \A_SPW_TOP|tx_data|mem[4][4]~q ;wire \A_SPW_TOP|tx_data|mem[12][4]~q ;wire \A_SPW_TOP|tx_data|mem[44][4]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[44][4]~q ;wire \A_SPW_TOP|tx_data|mem[36][4]~q ;wire \A_SPW_TOP|tx_data|Mux4~1_combout ;wire \A_SPW_TOP|tx_data|Mux4~4_combout ;wire \A_SPW_TOP|tx_data|Mux4~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~3_combout ;wire \u0|write_data_fifo_tx|data_out[3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[16][3]~q ;wire \A_SPW_TOP|tx_data|mem[18][3]~q ;wire \A_SPW_TOP|tx_data|mem[19][3]~q ;wire \A_SPW_TOP|tx_data|mem[17][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[17][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~5_combout ;wire \A_SPW_TOP|tx_data|mem[48][3]~q ;wire \A_SPW_TOP|tx_data|mem[50][3]~q ;wire \A_SPW_TOP|tx_data|mem[49][3]~q ;wire \A_SPW_TOP|tx_data|mem[51][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~7_combout ;wire \A_SPW_TOP|tx_data|mem[57][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[57][3]~q ;wire \A_SPW_TOP|tx_data|mem[58][3]~q ;wire \A_SPW_TOP|tx_data|mem[59][3]~q ;wire \A_SPW_TOP|tx_data|mem[56][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[56][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~8_combout ;wire \A_SPW_TOP|tx_data|mem[26][3]~q ;wire \A_SPW_TOP|tx_data|mem[25][3]~q ;wire \A_SPW_TOP|tx_data|mem[27][3]~q ;wire \A_SPW_TOP|tx_data|mem[24][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[24][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~6_combout ;wire \A_SPW_TOP|tx_data|Mux5~9_combout ;wire \A_SPW_TOP|tx_data|mem[52][3]~q ;wire \A_SPW_TOP|tx_data|mem[53][3]~q ;wire \A_SPW_TOP|tx_data|mem[21][3]~q ;wire \A_SPW_TOP|tx_data|mem[20][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[20][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~15_combout ;wire \A_SPW_TOP|tx_data|mem[28][3]~q ;wire \A_SPW_TOP|tx_data|mem[60][3]~q ;wire \A_SPW_TOP|tx_data|mem[61][3]~q ;wire \A_SPW_TOP|tx_data|mem[29][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~16_combout ;wire \A_SPW_TOP|tx_data|mem[31][3]~q ;wire \A_SPW_TOP|tx_data|mem[30][3]~q ;wire \A_SPW_TOP|tx_data|mem[63][3]~q ;wire \A_SPW_TOP|tx_data|mem[62][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[62][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~18_combout ;wire \A_SPW_TOP|tx_data|mem[54][3]~q ;wire \A_SPW_TOP|tx_data|mem[22][3]~q ;wire \A_SPW_TOP|tx_data|mem[55][3]~q ;wire \A_SPW_TOP|tx_data|mem[23][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~17_combout ;wire \A_SPW_TOP|tx_data|Mux5~19_combout ;wire \A_SPW_TOP|tx_data|mem[2][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[2][3]~q ;wire \A_SPW_TOP|tx_data|mem[0][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[0][3]~q ;wire \A_SPW_TOP|tx_data|mem[3][3]~q ;wire \A_SPW_TOP|tx_data|mem[1][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~0_combout ;wire \A_SPW_TOP|tx_data|mem[10][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[10][3]~q ;wire \A_SPW_TOP|tx_data|mem[9][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[9][3]~q ;wire \A_SPW_TOP|tx_data|mem[8][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[8][3]~q ;wire \A_SPW_TOP|tx_data|mem[11][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~1_combout ;wire \A_SPW_TOP|tx_data|mem[41][3]~q ;wire \A_SPW_TOP|tx_data|mem[40][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[40][3]~q ;wire \A_SPW_TOP|tx_data|mem[43][3]~q ;wire \A_SPW_TOP|tx_data|mem[42][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~3_combout ;wire \A_SPW_TOP|tx_data|mem[32][3]~q ;wire \A_SPW_TOP|tx_data|mem[33][3]~q ;wire \A_SPW_TOP|tx_data|mem[34][3]~q ;wire \A_SPW_TOP|tx_data|mem[35][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~2_combout ;wire \A_SPW_TOP|tx_data|Mux5~4_combout ;wire \A_SPW_TOP|tx_data|mem[46][3]~q ;wire \A_SPW_TOP|tx_data|mem[44][3]~q ;wire \A_SPW_TOP|tx_data|mem[47][3]~q ;wire \A_SPW_TOP|tx_data|mem[45][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~13_combout ;wire \A_SPW_TOP|tx_data|mem[6][3]~q ;wire \A_SPW_TOP|tx_data|mem[5][3]~feeder_combout ;wire \A_SPW_TOP|tx_data|mem[5][3]~q ;wire \A_SPW_TOP|tx_data|mem[7][3]~q ;wire \A_SPW_TOP|tx_data|mem[4][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~10_combout ;wire \A_SPW_TOP|tx_data|mem[14][3]~q ;wire \A_SPW_TOP|tx_data|mem[13][3]~q ;wire \A_SPW_TOP|tx_data|mem[15][3]~q ;wire \A_SPW_TOP|tx_data|mem[12][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~11_combout ;wire \A_SPW_TOP|tx_data|mem[36][3]~q ;wire \A_SPW_TOP|tx_data|mem[37][3]~q ;wire \A_SPW_TOP|tx_data|mem[39][3]~q ;wire \A_SPW_TOP|tx_data|mem[38][3]~q ;wire \A_SPW_TOP|tx_data|Mux5~12_combout ;wire \A_SPW_TOP|tx_data|Mux5~14_combout ;wire \A_SPW_TOP|tx_data|Mux5~20_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~8_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~4_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~5_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~4_combout ;wire \A_SPW_TOP|SPW|TX|Equal4~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~26_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~21_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~16_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~22_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~12_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~9_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~13_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~14_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~11_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~15_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~17_combout ;wire \A_SPW_TOP|SPW|TX|always3~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~18_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_data~19_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~6_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~7_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~8_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~10_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_null~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_null~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_fct~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~11_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~12_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~13_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout~0_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout~2_combout ;wire \A_SPW_TOP|SPW|TX|last_tx_sout~q ;wire \A_SPW_TOP|SPW|TX|tx_dout~16_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~18_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~19_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~22_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~20_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~21_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~14_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~15_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout~17_combout ;wire \A_SPW_TOP|SPW|TX|last_tx_dout~q ;wire \A_SPW_TOP|SPW|TX|tx_sout~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_sout_e~q ;wire \m_x|always3~0_combout ;wire \m_x|control_l_r[1]~feeder_combout ;wire \m_x|info[11]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][11]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][11]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~16_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \m_x|control_l_r[0]~feeder_combout ;wire \m_x|info[10]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][10]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~10_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][10]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|log2ceil~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add5~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector11~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|src_payload~13_combout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \m_x|info[9]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][9]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][9]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_payload~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~94_combout ;wire \m_x|info[8]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][8]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~95_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][8]~q ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~10_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag[8]~1_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag[8]~2_combout ;wire \A_SPW_TOP|rx_data|Add0~21_sumout ;wire \A_SPW_TOP|rx_data|Add0~22 ;wire \A_SPW_TOP|rx_data|Add0~17_sumout ;wire \A_SPW_TOP|rx_data|Add0~18 ;wire \A_SPW_TOP|rx_data|Add0~13_sumout ;wire \A_SPW_TOP|rx_data|Add0~14 ;wire \A_SPW_TOP|rx_data|Add0~9_sumout ;wire \A_SPW_TOP|rx_data|Add0~10 ;wire \A_SPW_TOP|rx_data|Add0~5_sumout ;wire \A_SPW_TOP|rx_data|Decoder0~4_combout ;wire \A_SPW_TOP|rx_data|Add0~6 ;wire \A_SPW_TOP|rx_data|Add0~1_sumout ;wire \A_SPW_TOP|rx_data|Decoder0~24_combout ;wire \A_SPW_TOP|rx_data|Decoder0~29_combout ;wire \A_SPW_TOP|rx_data|mem[44][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~43_combout ;wire \A_SPW_TOP|rx_data|Decoder0~47_combout ;wire \A_SPW_TOP|rx_data|mem[42][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~1_combout ;wire \A_SPW_TOP|rx_data|Decoder0~6_combout ;wire \A_SPW_TOP|rx_data|mem[40][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~61_combout ;wire \A_SPW_TOP|rx_data|Decoder0~77_combout ;wire \A_SPW_TOP|rx_data|mem[46][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~3_combout ;wire \A_SPW_TOP|rx_data|mem[36][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~84_combout ;wire \A_SPW_TOP|rx_data|Decoder0~26_combout ;wire \A_SPW_TOP|rx_data|Decoder0~0_combout ;wire \A_SPW_TOP|rx_data|Decoder0~27_combout ;wire \A_SPW_TOP|rx_data|mem[36][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~81_combout ;wire \A_SPW_TOP|rx_data|Decoder0~45_combout ;wire \A_SPW_TOP|rx_data|mem[34][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~3_combout ;wire \A_SPW_TOP|rx_data|mem[32][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~67_combout ;wire \A_SPW_TOP|rx_data|mem[38][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~1_combout ;wire \A_SPW_TOP|rx_data|Decoder0~2_combout ;wire \A_SPW_TOP|rx_data|mem[0][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~25_combout ;wire \A_SPW_TOP|rx_data|mem[4][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~62_combout ;wire \A_SPW_TOP|rx_data|mem[6][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~44_combout ;wire \A_SPW_TOP|rx_data|mem[2][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~0_combout ;wire \A_SPW_TOP|rx_data|mem[8][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~82_combout ;wire \A_SPW_TOP|rx_data|Decoder0~5_combout ;wire \A_SPW_TOP|rx_data|mem[8][8]~q ;wire \A_SPW_TOP|rx_data|mem[12][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~28_combout ;wire \A_SPW_TOP|rx_data|mem[12][8]~q ;wire \A_SPW_TOP|rx_data|mem[10][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~46_combout ;wire \A_SPW_TOP|rx_data|mem[10][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~71_combout ;wire \A_SPW_TOP|rx_data|mem[14][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~2_combout ;wire \A_SPW_TOP|rx_data|Mux0~4_combout ;wire \A_SPW_TOP|rx_data|mem[13][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~36_combout ;wire \A_SPW_TOP|rx_data|Decoder0~37_combout ;wire \A_SPW_TOP|rx_data|mem[13][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~17_combout ;wire \A_SPW_TOP|rx_data|Decoder0~18_combout ;wire \A_SPW_TOP|rx_data|mem[9][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~73_combout ;wire \A_SPW_TOP|rx_data|Decoder0~74_combout ;wire \A_SPW_TOP|rx_data|mem[15][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~52_combout ;wire \A_SPW_TOP|rx_data|Decoder0~55_combout ;wire \A_SPW_TOP|rx_data|mem[11][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~12_combout ;wire \A_SPW_TOP|rx_data|Decoder0~53_combout ;wire \A_SPW_TOP|rx_data|mem[3][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~86_combout ;wire \A_SPW_TOP|rx_data|Decoder0~34_combout ;wire \A_SPW_TOP|rx_data|mem[5][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~83_combout ;wire \A_SPW_TOP|rx_data|Decoder0~15_combout ;wire \A_SPW_TOP|rx_data|mem[1][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~64_combout ;wire \A_SPW_TOP|rx_data|mem[7][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~10_combout ;wire \A_SPW_TOP|rx_data|mem[33][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~16_combout ;wire \A_SPW_TOP|rx_data|mem[33][8]~q ;wire \A_SPW_TOP|rx_data|mem[37][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~35_combout ;wire \A_SPW_TOP|rx_data|mem[37][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~69_combout ;wire \A_SPW_TOP|rx_data|mem[39][8]~q ;wire \A_SPW_TOP|rx_data|mem[35][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~54_combout ;wire \A_SPW_TOP|rx_data|mem[35][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~11_combout ;wire \A_SPW_TOP|rx_data|Decoder0~56_combout ;wire \A_SPW_TOP|rx_data|mem[43][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~19_combout ;wire \A_SPW_TOP|rx_data|mem[41][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~79_combout ;wire \A_SPW_TOP|rx_data|mem[47][8]~q ;wire \A_SPW_TOP|rx_data|mem[45][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~38_combout ;wire \A_SPW_TOP|rx_data|mem[45][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~13_combout ;wire \A_SPW_TOP|rx_data|Mux0~14_combout ;wire \A_SPW_TOP|rx_data|Decoder0~9_combout ;wire \A_SPW_TOP|rx_data|Decoder0~20_combout ;wire \A_SPW_TOP|rx_data|mem[17][8]~q ;wire \A_SPW_TOP|rx_data|mem[25][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~13_combout ;wire \A_SPW_TOP|rx_data|Decoder0~22_combout ;wire \A_SPW_TOP|rx_data|mem[25][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~23_combout ;wire \A_SPW_TOP|rx_data|mem[57][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~21_combout ;wire \A_SPW_TOP|rx_data|mem[49][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~15_combout ;wire \A_SPW_TOP|rx_data|Decoder0~75_combout ;wire \A_SPW_TOP|rx_data|Decoder0~76_combout ;wire \A_SPW_TOP|rx_data|mem[31][8]~q ;wire \A_SPW_TOP|rx_data|mem[55][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~65_combout ;wire \A_SPW_TOP|rx_data|Decoder0~70_combout ;wire \A_SPW_TOP|rx_data|mem[55][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~66_combout ;wire \A_SPW_TOP|rx_data|mem[23][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~80_combout ;wire \A_SPW_TOP|rx_data|mem[63][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~18_combout ;wire \A_SPW_TOP|rx_data|Decoder0~7_combout ;wire \A_SPW_TOP|rx_data|Decoder0~58_combout ;wire \A_SPW_TOP|rx_data|mem[51][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~11_combout ;wire \A_SPW_TOP|rx_data|Decoder0~59_combout ;wire \A_SPW_TOP|rx_data|mem[27][8]~q ;wire \A_SPW_TOP|rx_data|mem[19][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~57_combout ;wire \A_SPW_TOP|rx_data|mem[19][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~60_combout ;wire \A_SPW_TOP|rx_data|mem[59][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~16_combout ;wire \A_SPW_TOP|rx_data|Decoder0~39_combout ;wire \A_SPW_TOP|rx_data|mem[21][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~41_combout ;wire \A_SPW_TOP|rx_data|mem[29][8]~q ;wire \A_SPW_TOP|rx_data|mem[53][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~40_combout ;wire \A_SPW_TOP|rx_data|mem[53][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~42_combout ;wire \A_SPW_TOP|rx_data|mem[61][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~17_combout ;wire \A_SPW_TOP|rx_data|Mux0~19_combout ;wire \A_SPW_TOP|rx_data|Decoder0~68_combout ;wire \A_SPW_TOP|rx_data|mem[54][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~72_combout ;wire \A_SPW_TOP|rx_data|mem[30][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~78_combout ;wire \A_SPW_TOP|rx_data|mem[62][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~63_combout ;wire \A_SPW_TOP|rx_data|mem[22][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~8_combout ;wire \A_SPW_TOP|rx_data|mem[16][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~8_combout ;wire \A_SPW_TOP|rx_data|mem[16][8]~q ;wire \A_SPW_TOP|rx_data|mem[24][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~12_combout ;wire \A_SPW_TOP|rx_data|mem[24][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~14_combout ;wire \A_SPW_TOP|rx_data|mem[56][8]~q ;wire \A_SPW_TOP|rx_data|mem[48][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~10_combout ;wire \A_SPW_TOP|rx_data|mem[48][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~5_combout ;wire \A_SPW_TOP|rx_data|mem[50][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~49_combout ;wire \A_SPW_TOP|rx_data|mem[50][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~50_combout ;wire \A_SPW_TOP|rx_data|mem[26][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~51_combout ;wire \A_SPW_TOP|rx_data|mem[58][8]~q ;wire \A_SPW_TOP|rx_data|mem[18][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~48_combout ;wire \A_SPW_TOP|rx_data|mem[18][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~6_combout ;wire \A_SPW_TOP|rx_data|mem[52][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~31_combout ;wire \A_SPW_TOP|rx_data|mem[52][8]~q ;wire \A_SPW_TOP|rx_data|mem[28][8]~feeder_combout ;wire \A_SPW_TOP|rx_data|Decoder0~85_combout ;wire \A_SPW_TOP|rx_data|Decoder0~32_combout ;wire \A_SPW_TOP|rx_data|mem[28][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~33_combout ;wire \A_SPW_TOP|rx_data|mem[60][8]~q ;wire \A_SPW_TOP|rx_data|Decoder0~30_combout ;wire \A_SPW_TOP|rx_data|mem[20][8]~q ;wire \A_SPW_TOP|rx_data|Mux0~7_combout ;wire \A_SPW_TOP|rx_data|Mux0~9_combout ;wire \A_SPW_TOP|rx_data|Mux0~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~15_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~17_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~18_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_003|src_payload~12_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][8]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|always4~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~93_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[8]~96_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add6~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~89_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~90_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~9_combout ;wire \A_SPW_TOP|rx_data|mem[2][7]~q ;wire \A_SPW_TOP|rx_data|mem[19][7]~q ;wire \A_SPW_TOP|rx_data|mem[18][7]~q ;wire \A_SPW_TOP|rx_data|mem[3][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~2_combout ;wire \A_SPW_TOP|rx_data|mem[4][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[4][7]~q ;wire \A_SPW_TOP|rx_data|mem[20][7]~q ;wire \A_SPW_TOP|rx_data|mem[21][7]~q ;wire \A_SPW_TOP|rx_data|mem[5][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~1_combout ;wire \A_SPW_TOP|rx_data|mem[16][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][7]~q ;wire \A_SPW_TOP|rx_data|mem[1][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[1][7]~q ;wire \A_SPW_TOP|rx_data|mem[0][7]~q ;wire \A_SPW_TOP|rx_data|mem[17][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~0_combout ;wire \A_SPW_TOP|rx_data|mem[7][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[7][7]~q ;wire \A_SPW_TOP|rx_data|mem[6][7]~q ;wire \A_SPW_TOP|rx_data|mem[22][7]~q ;wire \A_SPW_TOP|rx_data|mem[23][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~3_combout ;wire \A_SPW_TOP|rx_data|Mux1~4_combout ;wire \A_SPW_TOP|rx_data|mem[13][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][7]~q ;wire \A_SPW_TOP|rx_data|mem[28][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][7]~q ;wire \A_SPW_TOP|rx_data|mem[12][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[12][7]~q ;wire \A_SPW_TOP|rx_data|mem[29][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~11_combout ;wire \A_SPW_TOP|rx_data|mem[9][7]~q ;wire \A_SPW_TOP|rx_data|mem[8][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][7]~q ;wire \A_SPW_TOP|rx_data|mem[25][7]~q ;wire \A_SPW_TOP|rx_data|mem[24][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~10_combout ;wire \A_SPW_TOP|rx_data|mem[26][7]~q ;wire \A_SPW_TOP|rx_data|mem[11][7]~q ;wire \A_SPW_TOP|rx_data|mem[27][7]~q ;wire \A_SPW_TOP|rx_data|mem[10][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~12_combout ;wire \A_SPW_TOP|rx_data|mem[14][7]~q ;wire \A_SPW_TOP|rx_data|mem[15][7]~q ;wire \A_SPW_TOP|rx_data|mem[31][7]~q ;wire \A_SPW_TOP|rx_data|mem[30][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~13_combout ;wire \A_SPW_TOP|rx_data|Mux1~14_combout ;wire \A_SPW_TOP|rx_data|mem[41][7]~q ;wire \A_SPW_TOP|rx_data|mem[40][7]~q ;wire \A_SPW_TOP|rx_data|mem[57][7]~q ;wire \A_SPW_TOP|rx_data|mem[56][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[56][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~15_combout ;wire \A_SPW_TOP|rx_data|mem[58][7]~q ;wire \A_SPW_TOP|rx_data|mem[43][7]~q ;wire \A_SPW_TOP|rx_data|mem[59][7]~q ;wire \A_SPW_TOP|rx_data|mem[42][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[42][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~17_combout ;wire \A_SPW_TOP|rx_data|mem[60][7]~q ;wire \A_SPW_TOP|rx_data|mem[44][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[44][7]~q ;wire \A_SPW_TOP|rx_data|mem[61][7]~q ;wire \A_SPW_TOP|rx_data|mem[45][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~16_combout ;wire \A_SPW_TOP|rx_data|mem[47][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[47][7]~q ;wire \A_SPW_TOP|rx_data|mem[46][7]~q ;wire \A_SPW_TOP|rx_data|mem[62][7]~q ;wire \A_SPW_TOP|rx_data|mem[63][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~18_combout ;wire \A_SPW_TOP|rx_data|Mux1~19_combout ;wire \A_SPW_TOP|rx_data|mem[52][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[52][7]~q ;wire \A_SPW_TOP|rx_data|mem[37][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[37][7]~q ;wire \A_SPW_TOP|rx_data|mem[53][7]~q ;wire \A_SPW_TOP|rx_data|mem[36][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[36][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~6_combout ;wire \A_SPW_TOP|rx_data|mem[33][7]~q ;wire \A_SPW_TOP|rx_data|mem[32][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[32][7]~q ;wire \A_SPW_TOP|rx_data|mem[48][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[48][7]~q ;wire \A_SPW_TOP|rx_data|mem[49][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~5_combout ;wire \A_SPW_TOP|rx_data|mem[39][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[39][7]~q ;wire \A_SPW_TOP|rx_data|mem[54][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][7]~q ;wire \A_SPW_TOP|rx_data|mem[55][7]~q ;wire \A_SPW_TOP|rx_data|mem[38][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~8_combout ;wire \A_SPW_TOP|rx_data|mem[50][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][7]~q ;wire \A_SPW_TOP|rx_data|mem[35][7]~q ;wire \A_SPW_TOP|rx_data|mem[51][7]~q ;wire \A_SPW_TOP|rx_data|mem[34][7]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][7]~q ;wire \A_SPW_TOP|rx_data|Mux1~7_combout ;wire \A_SPW_TOP|rx_data|Mux1~9_combout ;wire \A_SPW_TOP|rx_data|Mux1~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~91_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~92_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][7]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][7]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[7]~217_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Selector2~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Decoder0~1_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~66 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~9_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[4]~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector25~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~10 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~17_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector23~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~18 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~13_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector22~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~14 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~25_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector21~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~26 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~21_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector20~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~22 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~41_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector19~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~42 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~37_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector18~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~38 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~33_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector17~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~34 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~49_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector16~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~50 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~29_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector15~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~30 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~45_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector14~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~46 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~62 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~53_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector12~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|router|Equal16~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|saved_grant[1]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~85_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~86_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~8_combout ;wire \A_SPW_TOP|rx_data|mem[13][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][6]~q ;wire \A_SPW_TOP|rx_data|mem[37][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[37][6]~q ;wire \A_SPW_TOP|rx_data|mem[5][6]~q ;wire \A_SPW_TOP|rx_data|mem[45][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~7_combout ;wire \A_SPW_TOP|rx_data|mem[52][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[52][6]~q ;wire \A_SPW_TOP|rx_data|mem[20][6]~q ;wire \A_SPW_TOP|rx_data|mem[28][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][6]~q ;wire \A_SPW_TOP|rx_data|mem[60][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~6_combout ;wire \A_SPW_TOP|rx_data|mem[29][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[29][6]~q ;wire \A_SPW_TOP|rx_data|mem[21][6]~q ;wire \A_SPW_TOP|rx_data|mem[61][6]~q ;wire \A_SPW_TOP|rx_data|mem[53][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~8_combout ;wire \A_SPW_TOP|rx_data|mem[36][6]~q ;wire \A_SPW_TOP|rx_data|mem[4][6]~q ;wire \A_SPW_TOP|rx_data|mem[44][6]~q ;wire \A_SPW_TOP|rx_data|mem[12][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[12][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~5_combout ;wire \A_SPW_TOP|rx_data|Mux2~9_combout ;wire \A_SPW_TOP|rx_data|mem[16][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][6]~q ;wire \A_SPW_TOP|rx_data|mem[48][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[48][6]~q ;wire \A_SPW_TOP|rx_data|mem[56][6]~q ;wire \A_SPW_TOP|rx_data|mem[24][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~1_combout ;wire \A_SPW_TOP|rx_data|mem[49][6]~q ;wire \A_SPW_TOP|rx_data|mem[25][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[25][6]~q ;wire \A_SPW_TOP|rx_data|mem[17][6]~q ;wire \A_SPW_TOP|rx_data|mem[57][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~3_combout ;wire \A_SPW_TOP|rx_data|mem[33][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[33][6]~q ;wire \A_SPW_TOP|rx_data|mem[9][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[9][6]~q ;wire \A_SPW_TOP|rx_data|mem[41][6]~q ;wire \A_SPW_TOP|rx_data|mem[1][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~2_combout ;wire \A_SPW_TOP|rx_data|mem[32][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[32][6]~q ;wire \A_SPW_TOP|rx_data|mem[8][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][6]~q ;wire \A_SPW_TOP|rx_data|mem[40][6]~q ;wire \A_SPW_TOP|rx_data|mem[0][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~0_combout ;wire \A_SPW_TOP|rx_data|Mux2~4_combout ;wire \A_SPW_TOP|rx_data|mem[47][6]~q ;wire \A_SPW_TOP|rx_data|mem[62][6]~q ;wire \A_SPW_TOP|rx_data|mem[46][6]~q ;wire \A_SPW_TOP|rx_data|mem[63][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~18_combout ;wire \A_SPW_TOP|rx_data|mem[39][6]~q ;wire \A_SPW_TOP|rx_data|mem[38][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[38][6]~q ;wire \A_SPW_TOP|rx_data|mem[54][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][6]~q ;wire \A_SPW_TOP|rx_data|mem[55][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~16_combout ;wire \A_SPW_TOP|rx_data|mem[22][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[22][6]~q ;wire \A_SPW_TOP|rx_data|mem[7][6]~q ;wire \A_SPW_TOP|rx_data|mem[6][6]~q ;wire \A_SPW_TOP|rx_data|mem[23][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~15_combout ;wire \A_SPW_TOP|rx_data|mem[30][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[30][6]~q ;wire \A_SPW_TOP|rx_data|mem[15][6]~q ;wire \A_SPW_TOP|rx_data|mem[31][6]~q ;wire \A_SPW_TOP|rx_data|mem[14][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~17_combout ;wire \A_SPW_TOP|rx_data|Mux2~19_combout ;wire \A_SPW_TOP|rx_data|mem[18][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[18][6]~q ;wire \A_SPW_TOP|rx_data|mem[50][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][6]~q ;wire \A_SPW_TOP|rx_data|mem[58][6]~q ;wire \A_SPW_TOP|rx_data|mem[26][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~11_combout ;wire \A_SPW_TOP|rx_data|mem[35][6]~q ;wire \A_SPW_TOP|rx_data|mem[11][6]~q ;wire \A_SPW_TOP|rx_data|mem[3][6]~q ;wire \A_SPW_TOP|rx_data|mem[43][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~12_combout ;wire \A_SPW_TOP|rx_data|mem[10][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][6]~q ;wire \A_SPW_TOP|rx_data|mem[2][6]~q ;wire \A_SPW_TOP|rx_data|mem[34][6]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][6]~q ;wire \A_SPW_TOP|rx_data|mem[42][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~10_combout ;wire \A_SPW_TOP|rx_data|mem[51][6]~q ;wire \A_SPW_TOP|rx_data|mem[19][6]~q ;wire \A_SPW_TOP|rx_data|mem[27][6]~q ;wire \A_SPW_TOP|rx_data|mem[59][6]~q ;wire \A_SPW_TOP|rx_data|Mux2~13_combout ;wire \A_SPW_TOP|rx_data|Mux2~14_combout ;wire \A_SPW_TOP|rx_data|Mux2~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~87_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~88_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][6]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][6]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[6]~221_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_020|update_grant~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~16_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~14_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~13_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~17_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_020|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_tx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~75_combout ;wire \m_x|last_is_data~0_combout ;wire \m_x|last_is_data~q ;wire \m_x|last_is_control~0_combout ;wire \m_x|last_is_control~q ;wire \m_x|always9~5_combout ;wire \m_x|last_was_data~q ;wire \m_x|bit_d_0~q ;wire \m_x|bit_d_2~feeder_combout ;wire \m_x|bit_d_2~q ;wire \m_x|bit_d_4~feeder_combout ;wire \m_x|bit_d_4~q ;wire \m_x|bit_d_6~q ;wire \m_x|bit_d_8~feeder_combout ;wire \m_x|bit_d_8~q ;wire \m_x|data~10_combout ;wire \m_x|data[8]~feeder_combout ;wire \m_x|last_is_timec~0_combout ;wire \m_x|last_is_timec~q ;wire \m_x|data[8]~1_combout ;wire \m_x|data[8]~2_combout ;wire \m_x|bit_d_1~feeder_combout ;wire \m_x|bit_d_1~q ;wire \m_x|bit_d_3~q ;wire \m_x|dta_timec[4]~feeder_combout ;wire \m_x|timecode[7]~0_combout ;wire \m_x|timecode[5]~feeder_combout ;wire \m_x|dta_timec[7]~feeder_combout ;wire \m_x|timecode[7]~feeder_combout ;wire \m_x|timecode[6]~feeder_combout ;wire \m_x|bit_d_5~q ;wire \m_x|dta_timec[2]~feeder_combout ;wire \m_x|timecode[3]~feeder_combout ;wire \m_x|always9~0_combout ;wire \m_x|last_was_control~q ;wire \m_x|last_was_timec~q ;wire \m_x|bit_d_7~q ;wire \m_x|always9~1_combout ;wire \m_x|rx_error~8_combout ;wire \m_x|data~0_combout ;wire \m_x|data_l_r[3]~feeder_combout ;wire \m_x|data_l_r[7]~1_combout ;wire \m_x|data~3_combout ;wire \m_x|data[2]~feeder_combout ;wire \m_x|dta_timec_p[4]~feeder_combout ;wire \m_x|data~7_combout ;wire \m_x|data_l_r[4]~feeder_combout ;wire \m_x|data~8_combout ;wire \m_x|data~4_combout ;wire \m_x|data~6_combout ;wire \m_x|data~5_combout ;wire \m_x|data[6]~feeder_combout ;wire \m_x|data_l_r[6]~feeder_combout ;wire \m_x|always9~3_combout ;wire \m_x|data~9_combout ;wire \m_x|always9~4_combout ;wire \m_x|rx_error~1_combout ;wire \m_x|always9~2_combout ;wire \m_x|rx_error~3_combout ;wire \m_x|rx_error~2_combout ;wire \m_x|rx_error~0_combout ;wire \m_x|rx_error~4_combout ;wire \m_x|rx_error~q ;wire \m_x|info[5]~feeder_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~79_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~77_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~7_combout ;wire \A_SPW_TOP|rx_data|mem[57][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[57][5]~q ;wire \A_SPW_TOP|rx_data|mem[61][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[61][5]~q ;wire \A_SPW_TOP|rx_data|mem[63][5]~q ;wire \A_SPW_TOP|rx_data|mem[59][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~18_combout ;wire \A_SPW_TOP|rx_data|mem[49][5]~q ;wire \A_SPW_TOP|rx_data|mem[51][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[51][5]~q ;wire \A_SPW_TOP|rx_data|mem[55][5]~q ;wire \A_SPW_TOP|rx_data|mem[53][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[53][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~16_combout ;wire \A_SPW_TOP|rx_data|mem[29][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[29][5]~q ;wire \A_SPW_TOP|rx_data|mem[27][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[27][5]~q ;wire \A_SPW_TOP|rx_data|mem[25][5]~q ;wire \A_SPW_TOP|rx_data|mem[31][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~17_combout ;wire \A_SPW_TOP|rx_data|mem[21][5]~q ;wire \A_SPW_TOP|rx_data|mem[19][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[19][5]~q ;wire \A_SPW_TOP|rx_data|mem[17][5]~q ;wire \A_SPW_TOP|rx_data|mem[23][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~15_combout ;wire \A_SPW_TOP|rx_data|Mux3~19_combout ;wire \A_SPW_TOP|rx_data|mem[45][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[45][5]~q ;wire \A_SPW_TOP|rx_data|mem[41][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[41][5]~q ;wire \A_SPW_TOP|rx_data|mem[43][5]~q ;wire \A_SPW_TOP|rx_data|mem[47][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~13_combout ;wire \A_SPW_TOP|rx_data|mem[35][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[35][5]~q ;wire \A_SPW_TOP|rx_data|mem[33][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[33][5]~q ;wire \A_SPW_TOP|rx_data|mem[37][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[37][5]~q ;wire \A_SPW_TOP|rx_data|mem[39][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~11_combout ;wire \A_SPW_TOP|rx_data|mem[5][5]~q ;wire \A_SPW_TOP|rx_data|mem[1][5]~q ;wire \A_SPW_TOP|rx_data|mem[7][5]~q ;wire \A_SPW_TOP|rx_data|mem[3][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~10_combout ;wire \A_SPW_TOP|rx_data|mem[9][5]~q ;wire \A_SPW_TOP|rx_data|mem[13][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][5]~q ;wire \A_SPW_TOP|rx_data|mem[15][5]~q ;wire \A_SPW_TOP|rx_data|mem[11][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[11][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~12_combout ;wire \A_SPW_TOP|rx_data|Mux3~14_combout ;wire \A_SPW_TOP|rx_data|mem[40][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[40][5]~q ;wire \A_SPW_TOP|rx_data|mem[42][5]~q ;wire \A_SPW_TOP|rx_data|mem[46][5]~q ;wire \A_SPW_TOP|rx_data|mem[44][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[44][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~3_combout ;wire \A_SPW_TOP|rx_data|mem[34][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][5]~q ;wire \A_SPW_TOP|rx_data|mem[32][5]~q ;wire \A_SPW_TOP|rx_data|mem[36][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[36][5]~q ;wire \A_SPW_TOP|rx_data|mem[38][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~1_combout ;wire \A_SPW_TOP|rx_data|mem[12][5]~q ;wire \A_SPW_TOP|rx_data|mem[10][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][5]~q ;wire \A_SPW_TOP|rx_data|mem[14][5]~q ;wire \A_SPW_TOP|rx_data|mem[8][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~2_combout ;wire \A_SPW_TOP|rx_data|mem[2][5]~q ;wire \A_SPW_TOP|rx_data|mem[4][5]~q ;wire \A_SPW_TOP|rx_data|mem[6][5]~q ;wire \A_SPW_TOP|rx_data|mem[0][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~0_combout ;wire \A_SPW_TOP|rx_data|Mux3~4_combout ;wire \A_SPW_TOP|rx_data|mem[26][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[26][5]~q ;wire \A_SPW_TOP|rx_data|mem[24][5]~q ;wire \A_SPW_TOP|rx_data|mem[30][5]~q ;wire \A_SPW_TOP|rx_data|mem[28][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~7_combout ;wire \A_SPW_TOP|rx_data|mem[18][5]~q ;wire \A_SPW_TOP|rx_data|mem[20][5]~q ;wire \A_SPW_TOP|rx_data|mem[16][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][5]~q ;wire \A_SPW_TOP|rx_data|mem[22][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~5_combout ;wire \A_SPW_TOP|rx_data|mem[52][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[52][5]~q ;wire \A_SPW_TOP|rx_data|mem[50][5]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][5]~q ;wire \A_SPW_TOP|rx_data|mem[54][5]~q ;wire \A_SPW_TOP|rx_data|mem[48][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~6_combout ;wire \A_SPW_TOP|rx_data|mem[56][5]~q ;wire \A_SPW_TOP|rx_data|mem[60][5]~q ;wire \A_SPW_TOP|rx_data|mem[62][5]~q ;wire \A_SPW_TOP|rx_data|mem[58][5]~q ;wire \A_SPW_TOP|rx_data|Mux3~8_combout ;wire \A_SPW_TOP|rx_data|Mux3~9_combout ;wire \A_SPW_TOP|rx_data|Mux3~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~78_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~80_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~82_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~81_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~83_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~15_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~17_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~18_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_021|src_payload~12_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|counter_rx_fifo|read_mux_out[5]~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][5]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][5]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~76_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[5]~84_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~65_combout ;wire \m_x|always0~0_combout ;wire \u0|counter_tx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~72_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~70_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|counter_rx_fifo|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~73_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~16_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~17_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~18_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~13_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|fsm_info|read_mux_out[4]~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~71_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~74_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~67_combout ;wire \u0|mm_interconnect_0|rsp_demux|src1_valid~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|led_pio_test|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~66_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~6_combout ;wire \A_SPW_TOP|rx_data|mem[58][4]~q ;wire \A_SPW_TOP|rx_data|mem[60][4]~q ;wire \A_SPW_TOP|rx_data|mem[56][4]~q ;wire \A_SPW_TOP|rx_data|mem[62][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~17_combout ;wire \A_SPW_TOP|rx_data|mem[41][4]~q ;wire \A_SPW_TOP|rx_data|mem[45][4]~q ;wire \A_SPW_TOP|rx_data|mem[43][4]~q ;wire \A_SPW_TOP|rx_data|mem[47][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[47][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~16_combout ;wire \A_SPW_TOP|rx_data|mem[57][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[57][4]~q ;wire \A_SPW_TOP|rx_data|mem[59][4]~q ;wire \A_SPW_TOP|rx_data|mem[63][4]~q ;wire \A_SPW_TOP|rx_data|mem[61][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~18_combout ;wire \A_SPW_TOP|rx_data|mem[42][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[42][4]~q ;wire \A_SPW_TOP|rx_data|mem[40][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[40][4]~q ;wire \A_SPW_TOP|rx_data|mem[46][4]~q ;wire \A_SPW_TOP|rx_data|mem[44][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~15_combout ;wire \A_SPW_TOP|rx_data|Mux4~19_combout ;wire \A_SPW_TOP|rx_data|mem[8][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][4]~q ;wire \A_SPW_TOP|rx_data|mem[24][4]~q ;wire \A_SPW_TOP|rx_data|mem[9][4]~q ;wire \A_SPW_TOP|rx_data|mem[25][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~10_combout ;wire \A_SPW_TOP|rx_data|mem[30][4]~q ;wire \A_SPW_TOP|rx_data|mem[14][4]~q ;wire \A_SPW_TOP|rx_data|mem[15][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[15][4]~q ;wire \A_SPW_TOP|rx_data|mem[31][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~13_combout ;wire \A_SPW_TOP|rx_data|mem[26][4]~q ;wire \A_SPW_TOP|rx_data|mem[10][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][4]~q ;wire \A_SPW_TOP|rx_data|mem[11][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[11][4]~q ;wire \A_SPW_TOP|rx_data|mem[27][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~12_combout ;wire \A_SPW_TOP|rx_data|mem[13][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][4]~q ;wire \A_SPW_TOP|rx_data|mem[12][4]~q ;wire \A_SPW_TOP|rx_data|mem[28][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][4]~q ;wire \A_SPW_TOP|rx_data|mem[29][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~11_combout ;wire \A_SPW_TOP|rx_data|Mux4~14_combout ;wire \A_SPW_TOP|rx_data|mem[52][4]~q ;wire \A_SPW_TOP|rx_data|mem[37][4]~q ;wire \A_SPW_TOP|rx_data|mem[53][4]~q ;wire \A_SPW_TOP|rx_data|mem[36][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[36][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~6_combout ;wire \A_SPW_TOP|rx_data|mem[32][4]~q ;wire \A_SPW_TOP|rx_data|mem[33][4]~q ;wire \A_SPW_TOP|rx_data|mem[48][4]~q ;wire \A_SPW_TOP|rx_data|mem[49][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~5_combout ;wire \A_SPW_TOP|rx_data|mem[50][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][4]~q ;wire \A_SPW_TOP|rx_data|mem[35][4]~q ;wire \A_SPW_TOP|rx_data|mem[34][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][4]~q ;wire \A_SPW_TOP|rx_data|mem[51][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~7_combout ;wire \A_SPW_TOP|rx_data|mem[38][4]~q ;wire \A_SPW_TOP|rx_data|mem[39][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[39][4]~q ;wire \A_SPW_TOP|rx_data|mem[54][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][4]~q ;wire \A_SPW_TOP|rx_data|mem[55][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~8_combout ;wire \A_SPW_TOP|rx_data|Mux4~9_combout ;wire \A_SPW_TOP|rx_data|mem[0][4]~q ;wire \A_SPW_TOP|rx_data|mem[16][4]~q ;wire \A_SPW_TOP|rx_data|mem[17][4]~q ;wire \A_SPW_TOP|rx_data|mem[1][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~0_combout ;wire \A_SPW_TOP|rx_data|mem[5][4]~q ;wire \A_SPW_TOP|rx_data|mem[20][4]~q ;wire \A_SPW_TOP|rx_data|mem[21][4]~q ;wire \A_SPW_TOP|rx_data|mem[4][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[4][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~1_combout ;wire \A_SPW_TOP|rx_data|mem[7][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[7][4]~q ;wire \A_SPW_TOP|rx_data|mem[6][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[6][4]~q ;wire \A_SPW_TOP|rx_data|mem[23][4]~q ;wire \A_SPW_TOP|rx_data|mem[22][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~3_combout ;wire \A_SPW_TOP|rx_data|mem[18][4]~q ;wire \A_SPW_TOP|rx_data|mem[3][4]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][4]~q ;wire \A_SPW_TOP|rx_data|mem[19][4]~q ;wire \A_SPW_TOP|rx_data|mem[2][4]~q ;wire \A_SPW_TOP|rx_data|Mux4~2_combout ;wire \A_SPW_TOP|rx_data|Mux4~4_combout ;wire \A_SPW_TOP|rx_data|Mux4~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~68_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~69_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][4]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][4]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[4]~225_combout ;wire \u0|mm_interconnect_0|router_001|Equal4~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_017|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_017|update_grant~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~55_combout ;wire \m_x|always10~0_combout ;wire \m_x|rx_got_null~0_combout ;wire \m_x|rx_got_time_code~1_combout ;wire \m_x|rx_got_null~q ;wire \m_x|info[3]~feeder_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~5_combout ;wire \A_SPW_TOP|rx_data|mem[48][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[48][3]~q ;wire \A_SPW_TOP|rx_data|mem[24][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][3]~q ;wire \A_SPW_TOP|rx_data|mem[16][3]~q ;wire \A_SPW_TOP|rx_data|mem[56][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~1_combout ;wire \A_SPW_TOP|rx_data|mem[49][3]~q ;wire \A_SPW_TOP|rx_data|mem[17][3]~q ;wire \A_SPW_TOP|rx_data|mem[25][3]~q ;wire \A_SPW_TOP|rx_data|mem[57][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~3_combout ;wire \A_SPW_TOP|rx_data|mem[32][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[32][3]~q ;wire \A_SPW_TOP|rx_data|mem[0][3]~q ;wire \A_SPW_TOP|rx_data|mem[40][3]~q ;wire \A_SPW_TOP|rx_data|mem[8][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~0_combout ;wire \A_SPW_TOP|rx_data|mem[9][3]~q ;wire \A_SPW_TOP|rx_data|mem[33][3]~q ;wire \A_SPW_TOP|rx_data|mem[41][3]~q ;wire \A_SPW_TOP|rx_data|mem[1][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[1][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~2_combout ;wire \A_SPW_TOP|rx_data|Mux5~4_combout ;wire \A_SPW_TOP|rx_data|mem[7][3]~q ;wire \A_SPW_TOP|rx_data|mem[39][3]~q ;wire \A_SPW_TOP|rx_data|mem[47][3]~q ;wire \A_SPW_TOP|rx_data|mem[15][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~17_combout ;wire \A_SPW_TOP|rx_data|mem[55][3]~q ;wire \A_SPW_TOP|rx_data|mem[31][3]~q ;wire \A_SPW_TOP|rx_data|mem[23][3]~q ;wire \A_SPW_TOP|rx_data|mem[63][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~18_combout ;wire \A_SPW_TOP|rx_data|mem[54][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][3]~q ;wire \A_SPW_TOP|rx_data|mem[22][3]~q ;wire \A_SPW_TOP|rx_data|mem[62][3]~q ;wire \A_SPW_TOP|rx_data|mem[30][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~16_combout ;wire \A_SPW_TOP|rx_data|mem[14][3]~q ;wire \A_SPW_TOP|rx_data|mem[38][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[38][3]~q ;wire \A_SPW_TOP|rx_data|mem[46][3]~q ;wire \A_SPW_TOP|rx_data|mem[6][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[6][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~15_combout ;wire \A_SPW_TOP|rx_data|Mux5~19_combout ;wire \A_SPW_TOP|rx_data|mem[36][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[36][3]~q ;wire \A_SPW_TOP|rx_data|mem[4][3]~q ;wire \A_SPW_TOP|rx_data|mem[44][3]~q ;wire \A_SPW_TOP|rx_data|mem[12][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[12][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~5_combout ;wire \A_SPW_TOP|rx_data|mem[21][3]~q ;wire \A_SPW_TOP|rx_data|mem[53][3]~q ;wire \A_SPW_TOP|rx_data|mem[29][3]~q ;wire \A_SPW_TOP|rx_data|mem[61][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~8_combout ;wire \A_SPW_TOP|rx_data|mem[37][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[37][3]~q ;wire \A_SPW_TOP|rx_data|mem[13][3]~q ;wire \A_SPW_TOP|rx_data|mem[45][3]~q ;wire \A_SPW_TOP|rx_data|mem[5][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~7_combout ;wire \A_SPW_TOP|rx_data|mem[28][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][3]~q ;wire \A_SPW_TOP|rx_data|mem[52][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[52][3]~q ;wire \A_SPW_TOP|rx_data|mem[60][3]~q ;wire \A_SPW_TOP|rx_data|mem[20][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~6_combout ;wire \A_SPW_TOP|rx_data|Mux5~9_combout ;wire \A_SPW_TOP|rx_data|mem[2][3]~q ;wire \A_SPW_TOP|rx_data|mem[10][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][3]~q ;wire \A_SPW_TOP|rx_data|mem[42][3]~q ;wire \A_SPW_TOP|rx_data|mem[34][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~10_combout ;wire \A_SPW_TOP|rx_data|mem[19][3]~q ;wire \A_SPW_TOP|rx_data|mem[27][3]~q ;wire \A_SPW_TOP|rx_data|mem[59][3]~q ;wire \A_SPW_TOP|rx_data|mem[51][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~13_combout ;wire \A_SPW_TOP|rx_data|mem[50][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][3]~q ;wire \A_SPW_TOP|rx_data|mem[18][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[18][3]~q ;wire \A_SPW_TOP|rx_data|mem[26][3]~q ;wire \A_SPW_TOP|rx_data|mem[58][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~11_combout ;wire \A_SPW_TOP|rx_data|mem[35][3]~q ;wire \A_SPW_TOP|rx_data|mem[11][3]~q ;wire \A_SPW_TOP|rx_data|mem[43][3]~q ;wire \A_SPW_TOP|rx_data|mem[3][3]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][3]~q ;wire \A_SPW_TOP|rx_data|Mux5~12_combout ;wire \A_SPW_TOP|rx_data|Mux5~14_combout ;wire \A_SPW_TOP|rx_data|Mux5~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~58_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~57_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~56_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~59_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~60_combout ;wire \u0|counter_tx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~62_combout ;wire \u0|fsm_info|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~61_combout ;wire \u0|counter_rx_fifo|read_mux_out[3]~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~63_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~64_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][3]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][3]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[3]~229_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~52_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~21_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~17_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|clock_sel|readdata[2]~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~53_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~54_combout ;wire \m_x|rx_got_nchar~0_combout ;wire \m_x|rx_got_nchar~1_combout ;wire \m_x|rx_got_nchar~q ;wire \m_x|info[2]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~44_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~43_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~4_combout ;wire \A_SPW_TOP|rx_data|mem[24][2]~q ;wire \A_SPW_TOP|rx_data|mem[26][2]~q ;wire \A_SPW_TOP|rx_data|mem[30][2]~q ;wire \A_SPW_TOP|rx_data|mem[28][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[28][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~7_combout ;wire \A_SPW_TOP|rx_data|mem[58][2]~q ;wire \A_SPW_TOP|rx_data|mem[56][2]~q ;wire \A_SPW_TOP|rx_data|mem[60][2]~q ;wire \A_SPW_TOP|rx_data|mem[62][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~8_combout ;wire \A_SPW_TOP|rx_data|mem[52][2]~q ;wire \A_SPW_TOP|rx_data|mem[50][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][2]~q ;wire \A_SPW_TOP|rx_data|mem[54][2]~q ;wire \A_SPW_TOP|rx_data|mem[48][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~6_combout ;wire \A_SPW_TOP|rx_data|mem[20][2]~q ;wire \A_SPW_TOP|rx_data|mem[18][2]~q ;wire \A_SPW_TOP|rx_data|mem[22][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[22][2]~q ;wire \A_SPW_TOP|rx_data|mem[16][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~5_combout ;wire \A_SPW_TOP|rx_data|Mux6~9_combout ;wire \A_SPW_TOP|rx_data|mem[12][2]~q ;wire \A_SPW_TOP|rx_data|mem[10][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][2]~q ;wire \A_SPW_TOP|rx_data|mem[14][2]~q ;wire \A_SPW_TOP|rx_data|mem[8][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~2_combout ;wire \A_SPW_TOP|rx_data|mem[34][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][2]~q ;wire \A_SPW_TOP|rx_data|mem[36][2]~q ;wire \A_SPW_TOP|rx_data|mem[38][2]~q ;wire \A_SPW_TOP|rx_data|mem[32][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~1_combout ;wire \A_SPW_TOP|rx_data|mem[42][2]~q ;wire \A_SPW_TOP|rx_data|mem[40][2]~q ;wire \A_SPW_TOP|rx_data|mem[46][2]~q ;wire \A_SPW_TOP|rx_data|mem[44][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~3_combout ;wire \A_SPW_TOP|rx_data|mem[0][2]~q ;wire \A_SPW_TOP|rx_data|mem[2][2]~q ;wire \A_SPW_TOP|rx_data|mem[6][2]~q ;wire \A_SPW_TOP|rx_data|mem[4][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~0_combout ;wire \A_SPW_TOP|rx_data|Mux6~4_combout ;wire \A_SPW_TOP|rx_data|mem[3][2]~q ;wire \A_SPW_TOP|rx_data|mem[1][2]~q ;wire \A_SPW_TOP|rx_data|mem[5][2]~q ;wire \A_SPW_TOP|rx_data|mem[7][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~10_combout ;wire \A_SPW_TOP|rx_data|mem[35][2]~q ;wire \A_SPW_TOP|rx_data|mem[33][2]~q ;wire \A_SPW_TOP|rx_data|mem[37][2]~q ;wire \A_SPW_TOP|rx_data|mem[39][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~11_combout ;wire \A_SPW_TOP|rx_data|mem[41][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[41][2]~q ;wire \A_SPW_TOP|rx_data|mem[43][2]~q ;wire \A_SPW_TOP|rx_data|mem[45][2]~q ;wire \A_SPW_TOP|rx_data|mem[47][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~13_combout ;wire \A_SPW_TOP|rx_data|mem[13][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][2]~q ;wire \A_SPW_TOP|rx_data|mem[9][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[9][2]~q ;wire \A_SPW_TOP|rx_data|mem[11][2]~q ;wire \A_SPW_TOP|rx_data|mem[15][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~12_combout ;wire \A_SPW_TOP|rx_data|Mux6~14_combout ;wire \A_SPW_TOP|rx_data|mem[53][2]~q ;wire \A_SPW_TOP|rx_data|mem[21][2]~q ;wire \A_SPW_TOP|rx_data|mem[29][2]~q ;wire \A_SPW_TOP|rx_data|mem[61][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~17_combout ;wire \A_SPW_TOP|rx_data|mem[25][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[25][2]~q ;wire \A_SPW_TOP|rx_data|mem[17][2]~q ;wire \A_SPW_TOP|rx_data|mem[49][2]~q ;wire \A_SPW_TOP|rx_data|mem[57][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~15_combout ;wire \A_SPW_TOP|rx_data|mem[19][2]~q ;wire \A_SPW_TOP|rx_data|mem[51][2]~q ;wire \A_SPW_TOP|rx_data|mem[59][2]~q ;wire \A_SPW_TOP|rx_data|mem[27][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~16_combout ;wire \A_SPW_TOP|rx_data|mem[31][2]~q ;wire \A_SPW_TOP|rx_data|mem[23][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[23][2]~q ;wire \A_SPW_TOP|rx_data|mem[63][2]~q ;wire \A_SPW_TOP|rx_data|mem[55][2]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[55][2]~q ;wire \A_SPW_TOP|rx_data|Mux6~18_combout ;wire \A_SPW_TOP|rx_data|Mux6~19_combout ;wire \A_SPW_TOP|rx_data|Mux6~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~45_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~46_combout ;wire \u0|counter_tx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~49_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~47_combout ;wire \u0|fsm_info|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~48_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|counter_rx_fifo|read_mux_out[2]~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~50_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~51_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][2]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][2]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[2]~233_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~2_combout ;wire \u0|mm_interconnect_0|router_001|Equal16~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal16~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|local_write~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|nonposted_write_endofpacket~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~35_combout ;wire \u0|counter_tx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~37_combout ;wire \u0|fsm_info|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~feeder_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~36_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|counter_rx_fifo|read_mux_out[1]~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~39_combout ;wire \m_x|rx_got_time_code~0_combout ;wire \m_x|rx_got_time_code~q ;wire \m_x|info[1]~feeder_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~40_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~1_combout ;wire \u0|clock_sel|always0~0_combout ;wire \u0|clock_sel|readdata[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~41_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~42_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~3_combout ;wire \A_SPW_TOP|rx_data|mem[41][1]~q ;wire \A_SPW_TOP|rx_data|mem[40][1]~q ;wire \A_SPW_TOP|rx_data|mem[57][1]~q ;wire \A_SPW_TOP|rx_data|mem[56][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~15_combout ;wire \A_SPW_TOP|rx_data|mem[46][1]~q ;wire \A_SPW_TOP|rx_data|mem[62][1]~q ;wire \A_SPW_TOP|rx_data|mem[63][1]~q ;wire \A_SPW_TOP|rx_data|mem[47][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[47][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~18_combout ;wire \A_SPW_TOP|rx_data|mem[60][1]~q ;wire \A_SPW_TOP|rx_data|mem[44][1]~q ;wire \A_SPW_TOP|rx_data|mem[45][1]~q ;wire \A_SPW_TOP|rx_data|mem[61][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~16_combout ;wire \A_SPW_TOP|rx_data|mem[42][1]~q ;wire \A_SPW_TOP|rx_data|mem[58][1]~q ;wire \A_SPW_TOP|rx_data|mem[59][1]~q ;wire \A_SPW_TOP|rx_data|mem[43][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~17_combout ;wire \A_SPW_TOP|rx_data|Mux7~19_combout ;wire \A_SPW_TOP|rx_data|mem[2][1]~q ;wire \A_SPW_TOP|rx_data|mem[18][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[18][1]~q ;wire \A_SPW_TOP|rx_data|mem[3][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][1]~q ;wire \A_SPW_TOP|rx_data|mem[19][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~2_combout ;wire \A_SPW_TOP|rx_data|mem[16][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][1]~q ;wire \A_SPW_TOP|rx_data|mem[1][1]~q ;wire \A_SPW_TOP|rx_data|mem[0][1]~q ;wire \A_SPW_TOP|rx_data|mem[17][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~0_combout ;wire \A_SPW_TOP|rx_data|mem[4][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[4][1]~q ;wire \A_SPW_TOP|rx_data|mem[20][1]~q ;wire \A_SPW_TOP|rx_data|mem[21][1]~q ;wire \A_SPW_TOP|rx_data|mem[5][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~1_combout ;wire \A_SPW_TOP|rx_data|mem[22][1]~q ;wire \A_SPW_TOP|rx_data|mem[6][1]~q ;wire \A_SPW_TOP|rx_data|mem[23][1]~q ;wire \A_SPW_TOP|rx_data|mem[7][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~3_combout ;wire \A_SPW_TOP|rx_data|Mux7~4_combout ;wire \A_SPW_TOP|rx_data|mem[30][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[30][1]~q ;wire \A_SPW_TOP|rx_data|mem[14][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[14][1]~q ;wire \A_SPW_TOP|rx_data|mem[31][1]~q ;wire \A_SPW_TOP|rx_data|mem[15][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~13_combout ;wire \A_SPW_TOP|rx_data|mem[26][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[26][1]~q ;wire \A_SPW_TOP|rx_data|mem[10][1]~q ;wire \A_SPW_TOP|rx_data|mem[11][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[11][1]~q ;wire \A_SPW_TOP|rx_data|mem[27][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~12_combout ;wire \A_SPW_TOP|rx_data|mem[12][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[12][1]~q ;wire \A_SPW_TOP|rx_data|mem[13][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[13][1]~q ;wire \A_SPW_TOP|rx_data|mem[28][1]~q ;wire \A_SPW_TOP|rx_data|mem[29][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~11_combout ;wire \A_SPW_TOP|rx_data|mem[24][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][1]~q ;wire \A_SPW_TOP|rx_data|mem[8][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[8][1]~q ;wire \A_SPW_TOP|rx_data|mem[9][1]~q ;wire \A_SPW_TOP|rx_data|mem[25][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~10_combout ;wire \A_SPW_TOP|rx_data|Mux7~14_combout ;wire \A_SPW_TOP|rx_data|mem[38][1]~q ;wire \A_SPW_TOP|rx_data|mem[39][1]~q ;wire \A_SPW_TOP|rx_data|mem[55][1]~q ;wire \A_SPW_TOP|rx_data|mem[54][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~8_combout ;wire \A_SPW_TOP|rx_data|mem[33][1]~q ;wire \A_SPW_TOP|rx_data|mem[48][1]~q ;wire \A_SPW_TOP|rx_data|mem[32][1]~q ;wire \A_SPW_TOP|rx_data|mem[49][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~5_combout ;wire \A_SPW_TOP|rx_data|mem[52][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[52][1]~q ;wire \A_SPW_TOP|rx_data|mem[36][1]~q ;wire \A_SPW_TOP|rx_data|mem[53][1]~q ;wire \A_SPW_TOP|rx_data|mem[37][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[37][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~6_combout ;wire \A_SPW_TOP|rx_data|mem[50][1]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[50][1]~q ;wire \A_SPW_TOP|rx_data|mem[34][1]~q ;wire \A_SPW_TOP|rx_data|mem[51][1]~q ;wire \A_SPW_TOP|rx_data|mem[35][1]~q ;wire \A_SPW_TOP|rx_data|Mux7~7_combout ;wire \A_SPW_TOP|rx_data|Mux7~9_combout ;wire \A_SPW_TOP|rx_data|Mux7~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~33_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~31_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~32_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~34_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][1]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][1]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[1]~237_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal8~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_019|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_019|src_payload~12_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fsm_info|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~1_combout ;wire \u0|auto_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src1_valid~combout ;wire \u0|counter_rx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~3_combout ;wire \u0|counter_tx_fifo|read_mux_out[0]~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~2_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~9_combout ;wire \u0|write_en_tx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~10_combout ;wire \u0|timecode_tx_enable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~11_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~0_combout ;wire \u0|clock_sel|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~12_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~13_combout ;wire \u0|link_disable|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~5_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~7_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~16_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_002|src_payload~12_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~0_combout ;wire \A_SPW_TOP|SPW|RX|rx_tick_out~q ;wire \u0|timecode_ready_rx|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~18_combout ;wire \u0|mm_interconnect_0|cmd_mux|src_payload~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~16_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~17_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~19_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][0]~q ;wire \m_x|rx_got_fct~0_combout ;wire \m_x|rx_got_fct~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~16_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~13_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_005|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_full_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~21_combout ;wire \u0|data_read_en_rx|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~20_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~14_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_006|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_rx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~22_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~16_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~15_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|cmd_mux_012|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_full_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~23_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~24_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~13_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~14_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~16_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~4_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~18_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~17_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_013|src_payload~12_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|fifo_empty_tx_status|read_mux_out~combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~26_combout ;wire \u0|link_start|readdata[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~25_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_data~4_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~0_combout ;wire \A_SPW_TOP|SPW|TX|ready_tx_timecode~q ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~12_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0]~feeder_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~15_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~16_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|ShiftLeft0~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|align_address_to_size|LessThan0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~13_sumout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~18_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~9_sumout ;wire \u0|mm_interconnect_0|cmd_mux_016|src_payload~17_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[1]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~10 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~5_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~6 ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add0~1_sumout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg~0_combout ;wire \u0|timecode_tx_ready|read_mux_out~combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~27_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~28_combout ;wire \A_SPW_TOP|SPW|RX|rx_data_flag~0_combout ;wire \A_SPW_TOP|rx_data|mem[21][0]~q ;wire \A_SPW_TOP|rx_data|mem[53][0]~q ;wire \A_SPW_TOP|rx_data|mem[29][0]~q ;wire \A_SPW_TOP|rx_data|mem[61][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~8_combout ;wire \A_SPW_TOP|rx_data|mem[52][0]~q ;wire \A_SPW_TOP|rx_data|mem[20][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[20][0]~q ;wire \A_SPW_TOP|rx_data|mem[60][0]~q ;wire \A_SPW_TOP|rx_data|mem[28][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~6_combout ;wire \A_SPW_TOP|rx_data|mem[12][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[12][0]~q ;wire \A_SPW_TOP|rx_data|mem[4][0]~q ;wire \A_SPW_TOP|rx_data|mem[36][0]~q ;wire \A_SPW_TOP|rx_data|mem[44][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~5_combout ;wire \A_SPW_TOP|rx_data|mem[13][0]~q ;wire \A_SPW_TOP|rx_data|mem[5][0]~q ;wire \A_SPW_TOP|rx_data|mem[45][0]~q ;wire \A_SPW_TOP|rx_data|mem[37][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~7_combout ;wire \A_SPW_TOP|rx_data|Mux8~9_combout ;wire \A_SPW_TOP|rx_data|mem[35][0]~q ;wire \A_SPW_TOP|rx_data|mem[11][0]~q ;wire \A_SPW_TOP|rx_data|mem[43][0]~q ;wire \A_SPW_TOP|rx_data|mem[3][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[3][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~12_combout ;wire \A_SPW_TOP|rx_data|mem[51][0]~q ;wire \A_SPW_TOP|rx_data|mem[27][0]~q ;wire \A_SPW_TOP|rx_data|mem[19][0]~q ;wire \A_SPW_TOP|rx_data|mem[59][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~13_combout ;wire \A_SPW_TOP|rx_data|mem[34][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[34][0]~q ;wire \A_SPW_TOP|rx_data|mem[10][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[10][0]~q ;wire \A_SPW_TOP|rx_data|mem[42][0]~q ;wire \A_SPW_TOP|rx_data|mem[2][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~10_combout ;wire \A_SPW_TOP|rx_data|mem[50][0]~q ;wire \A_SPW_TOP|rx_data|mem[18][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[18][0]~q ;wire \A_SPW_TOP|rx_data|mem[26][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[26][0]~q ;wire \A_SPW_TOP|rx_data|mem[58][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~11_combout ;wire \A_SPW_TOP|rx_data|Mux8~14_combout ;wire \A_SPW_TOP|rx_data|mem[1][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[1][0]~q ;wire \A_SPW_TOP|rx_data|mem[33][0]~q ;wire \A_SPW_TOP|rx_data|mem[41][0]~q ;wire \A_SPW_TOP|rx_data|mem[9][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[9][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~2_combout ;wire \A_SPW_TOP|rx_data|mem[17][0]~q ;wire \A_SPW_TOP|rx_data|mem[49][0]~q ;wire \A_SPW_TOP|rx_data|mem[25][0]~q ;wire \A_SPW_TOP|rx_data|mem[57][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~3_combout ;wire \A_SPW_TOP|rx_data|mem[16][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[16][0]~q ;wire \A_SPW_TOP|rx_data|mem[48][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[48][0]~q ;wire \A_SPW_TOP|rx_data|mem[56][0]~q ;wire \A_SPW_TOP|rx_data|mem[24][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[24][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~1_combout ;wire \A_SPW_TOP|rx_data|mem[0][0]~q ;wire \A_SPW_TOP|rx_data|mem[8][0]~q ;wire \A_SPW_TOP|rx_data|mem[40][0]~q ;wire \A_SPW_TOP|rx_data|mem[32][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[32][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~0_combout ;wire \A_SPW_TOP|rx_data|Mux8~4_combout ;wire \A_SPW_TOP|rx_data|mem[62][0]~q ;wire \A_SPW_TOP|rx_data|mem[46][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[46][0]~q ;wire \A_SPW_TOP|rx_data|mem[47][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[47][0]~q ;wire \A_SPW_TOP|rx_data|mem[63][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~18_combout ;wire \A_SPW_TOP|rx_data|mem[30][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[30][0]~q ;wire \A_SPW_TOP|rx_data|mem[14][0]~q ;wire \A_SPW_TOP|rx_data|mem[31][0]~q ;wire \A_SPW_TOP|rx_data|mem[15][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[15][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~17_combout ;wire \A_SPW_TOP|rx_data|mem[7][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[7][0]~q ;wire \A_SPW_TOP|rx_data|mem[6][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[6][0]~q ;wire \A_SPW_TOP|rx_data|mem[22][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[22][0]~q ;wire \A_SPW_TOP|rx_data|mem[23][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~15_combout ;wire \A_SPW_TOP|rx_data|mem[38][0]~q ;wire \A_SPW_TOP|rx_data|mem[54][0]~feeder_combout ;wire \A_SPW_TOP|rx_data|mem[54][0]~q ;wire \A_SPW_TOP|rx_data|mem[39][0]~q ;wire \A_SPW_TOP|rx_data|mem[55][0]~q ;wire \A_SPW_TOP|rx_data|Mux8~16_combout ;wire \A_SPW_TOP|rx_data|Mux8~19_combout ;wire \A_SPW_TOP|rx_data|Mux8~20_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[1][0]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem[0][0]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~29_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_data[0]~30_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~59_combout ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~56_combout ;wire \u0|mm_interconnect_0|rsp_demux_011|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~58_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~55_combout ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[116]~57_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_007|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~51_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~53_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~50_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~54_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[115]~52_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~54 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector11~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~2 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~57_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector10~0_combout ;wire \u0|mm_interconnect_0|router|Equal13~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src7_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|packet_in_progress~q ;wire \u0|mm_interconnect_0|cmd_mux_007|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][114]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~19_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~feeder_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][114]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~46_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~48_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~47_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~49_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[114]~45_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][113]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~18_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][113]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~44_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~40_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~42_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~43_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[113]~41_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|WideOr0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_015|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~39_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~38_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~37_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~36_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[112]~35_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][111]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~32_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~33_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~34_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~30_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[111]~31_combout ;wire \u0|mm_interconnect_0|router_001|Equal14~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal15~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|rsp_demux_009|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_009|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][110]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][110]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~27_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~29_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~25_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~26_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[110]~28_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][109]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~24_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~23_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~20_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~21_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[109]~22_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~9_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~2_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~10_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~3_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~5_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~12_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~feeder_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~6_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~8_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~7_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~11_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~9_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Add0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|cmd_demux|src10_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_010|saved_grant[0]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~feeder_combout ;wire \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux_010|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~17_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~18_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~16_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~15_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[108]~19_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal2~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src0_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][66]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~3_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][66]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_demux|src0_valid~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~10_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~14_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~13_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~11_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[107]~12_combout ;wire \u0|mm_interconnect_0|router_001|Equal1~0_combout ;wire \u0|mm_interconnect_0|router_001|Equal13~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src7_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_007|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][106]~q ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~11_combout ;wire \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][106]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~6_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~7_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~8_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~5_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[106]~9_combout ;wire \u0|mm_interconnect_0|router_001|src_data[103]~0_combout ;wire \u0|mm_interconnect_0|router_001|src_data[101]~3_combout ;wire \u0|mm_interconnect_0|router_001|src_data[104]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|router_001|src_data[100]~1_combout ;wire \u0|mm_interconnect_0|router_001|src_data[102]~2_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~6_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~3_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~4_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~5_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~3_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|response_sink_accepted~combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~12_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~9_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~6_combout ;wire \u0|mm_interconnect_0|router_001|Equal6~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~8_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~11_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~10_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~7_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~9_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|Add0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|nonposted_cmd_accepted~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_018|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|write~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[0]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_018|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~4_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~3_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~2_combout ;wire \u0|mm_interconnect_0|rsp_mux|src_data[105]~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~2_combout ;wire \u0|mm_interconnect_0|router|Equal7~4_combout ;wire \u0|mm_interconnect_0|router|Equal7~3_combout ;wire \u0|mm_interconnect_0|router|Equal7~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~8_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_valid~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|update_grant~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|packet_in_progress~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src18_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~7_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][76]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][77]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_busy~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][75]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~9_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][78]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add1~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|Add0~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|m0_write~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter[1]~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~2_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter~1_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ;wire \u0|mm_interconnect_0|router_001|Equal20~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][68]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~2_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~3_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ;wire \u0|mm_interconnect_0|router|src_data[104]~8_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~2_combout ;wire \u0|mm_interconnect_0|router|src_data[101]~7_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~1_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~1_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~2_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~3_combout ;wire \u0|mm_interconnect_0|router|src_data[100]~6_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~3_combout ;wire \u0|mm_interconnect_0|router|src_data[103]~0_combout ;wire \u0|mm_interconnect_0|router|Equal20~0_combout ;wire \u0|mm_interconnect_0|router|src_data[102]~5_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|Equal0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src9_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|src_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~3_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|WideOr0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~4_combout ;wire \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux|src_payload~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~2_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~26_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~27_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~25_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~21_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~22_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~23_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~24_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~19_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~20_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~17_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~18_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~28_combout ;wire \u0|mm_interconnect_0|rsp_demux_004|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_demux_007|src1_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~3_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~0_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~8_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~9_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~4_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~5_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~6_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~7_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~10_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~11_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~14_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~15_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][130]~q ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~8_combout ;wire \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][130]~q ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~12_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload~13_combout ;wire \u0|mm_interconnect_0|rsp_mux_001|src_payload[0]~16_combout ;wire \u0|mm_interconnect_0|router|Equal14~0_combout ;wire \u0|mm_interconnect_0|router|Equal14~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][68]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][69]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][69]~q ;wire \u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~feeder_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][129]~q ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|read~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[1]~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used[0]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ;wire \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~1_combout ;wire \u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~1_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~0_combout ;wire \u0|mm_interconnect_0|rsp_mux|WideOr1~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~6 ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add1~1_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~5_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[5]~4_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector24~1_combout ;wire \u0|mm_interconnect_0|router|Equal7~0_combout ;wire \u0|mm_interconnect_0|router|Equal7~5_combout ;wire \u0|mm_interconnect_0|router|Equal7~6_combout ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src14_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|WideOr1~combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_014|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][74]~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[1]~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux|sink_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_demux|WideOr0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Add0~61_sumout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|Selector13~0_combout ;wire \u0|mm_interconnect_0|router|Equal15~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src9_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|src9_valid~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[1]~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg[0]~2_combout ;wire \u0|mm_interconnect_0|cmd_mux_009|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ;wire \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|sink_ready~0_combout ;wire \u0|mm_interconnect_0|cmd_demux_001|WideOr0~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|suppress_change_dest_id~combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~0_combout ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ;wire \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ;wire \u0|mm_interconnect_0|router|Equal6~1_combout ;wire \u0|mm_interconnect_0|router|Equal6~0_combout ;wire \u0|mm_interconnect_0|cmd_demux|src18_valid~0_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|arb|grant[0]~1_combout ;wire \u0|mm_interconnect_0|cmd_mux_018|src_payload~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~41_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~17_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~42 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~1_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~2 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~5_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~8_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~6 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~13_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~10_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~14 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~18 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~10 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~37_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~16_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~38 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~21_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~12_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~22 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~30 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~33_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~15_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~34 ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~25_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~13_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|always4~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~17_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~11_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan1~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan10~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~29_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~14_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Equal2~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter[8]~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Add0~9_sumout ;wire \R_400_to_2_5_10_100_200_300MHZ|counter~9_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|LessThan11~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~3_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~6_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~4_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~2_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|Mux0~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~0_combout ;wire \R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~q ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~1_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~2_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~3_combout ;wire \A_SPW_TOP|SPW|TX|tx_dout_e~q ;wire \db_system_spwulight_b|PB_down~1_combout ;wire \db_system_spwulight_b|PB_down~q ;wire [9:0] \m_x|dta_timec ;wire [2:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|aligned_address_bits ;wire [3:0] \A_SPW_TOP|SPW|RX|control_r ;wire [9:0] \m_x|data_l_r ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [2:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [2:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [5:0] \m_x|counter_neg ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [5:0] \A_SPW_TOP|rx_data|wr_ptr ;wire [8:0] \A_SPW_TOP|SPW|RX|rx_data_flag ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [2:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_p_r ;wire [9:0] \A_SPW_TOP|SPW|RX|data_l_r ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [3:0] \m_x|control_l_r ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [3:0] \m_x|control_r ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [5:0] \A_SPW_TOP|rx_data|credit_counter ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [3:0] \m_x|control ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after64us ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter ;wire [3:0] \A_SPW_TOP|SPW|RX|control ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [10:0] \R_400_to_2_5_10_100_200_300MHZ|counter_100 ;wire [11:0] \A_SPW_TOP|SPW|FSM|after128us ;wire [2:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [5:0] \A_SPW_TOP|rx_data|rd_ptr ;wire [31:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|auto_start_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [3:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [7:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|led_pio_test_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [31:0] \u0|counter_tx_fifo|readdata ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [7:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [7:0] \u0|mm_interconnect_0|link_disable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [7:0] \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [0:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg ;wire [7:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [7:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [5:0] \A_SPW_TOP|SPW|TX|fct_counter_receive ;wire [7:0] \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_007|src_payload ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [7:0] \A_SPW_TOP|SPW|TX|last_timein_control_flag_tx ;wire [0:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_dest_id ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst ;wire [2:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|saved_grant ;wire [7:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|wait_latency_counter ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_014|src_payload ;wire [0:0] \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg ;wire [3:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_013|saved_grant ;wire [0:0] \u0|mm_interconnect_0|link_disable_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|saved_grant ;wire [128:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [7:0] \u0|mm_interconnect_0|write_en_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|saved_grant ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_017|saved_grant ;wire [128:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [3:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|av_readdata_pre ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_020|saved_grant ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|saved_grant ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_002|saved_grant ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used ;wire [2:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [11:0] \A_SPW_TOP|SPW|FSM|after850ns ;wire [15:0] \db_system_spwulight_b|counter ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_AWVALID ;wire [0:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_ARSIZE ;wire [2:0] \A_SPW_TOP|SPW|TX|fct_flag ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_translator|wait_latency_counter ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [7:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [7:0] \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|saved_grant ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [31:0] \u0|write_data_fifo_tx|readdata ;wire [2:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [31:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|av_readdata_pre ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_ARVALID ;wire [128:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_ARBURST ;wire [0:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WLAST ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_012|saved_grant ;wire [2:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [0:0] \u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg ;wire [1:0] \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [7:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|arb|top_priority_reg ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [3:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_ARLEN ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter ;wire [4:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_dest_id ;wire [3:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|rsp_mux_001|src_data ;wire [0:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|read_latency_shift_reg ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_ARID ;wire [2:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used ;wire [7:0] \u0|timecode_rx|read_mux_out ;wire [0:0] \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [128:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_004|saved_grant ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|av_readdata_pre ;wire [1:0] \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [3:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_rst_n ;wire [7:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_015|src_payload ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|saved_grant ;wire [13:0] \u0|data_info|read_mux_out ;wire [1:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [0:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_AWADDR ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_AWLEN ;wire [9:0] \A_SPW_TOP|SPW|RX|dta_timec_p ;wire [31:0] \u0|timecode_ready_rx|readdata ;wire [5:0] \A_SPW_TOP|tx_data|wr_ptr ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [3:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [9:0] \A_SPW_TOP|SPW|RX|data ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|hps_0|fpga_interfaces|h2f_AWBURST ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [31:0] \u0|hps_0|fpga_interfaces|h2f_WDATA ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|wait_latency_counter ;wire [31:0] \u0|mm_interconnect_0|fsm_info_s1_translator|av_readdata_pre ;wire [3:0] \m_x|control_p_r ;wire [0:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|read_latency_shift_reg ;wire [3:0] \u0|hps_0|fpga_interfaces|h2f_WSTRB ;wire [4:0] \u0|led_pio_test|data_out ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter ;wire [9:0] \m_x|data ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_010|src_payload ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_016|saved_grant ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used ;wire [0:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|read_latency_shift_reg ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [3:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_005|saved_grant ;wire [1:0] \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain ;wire [128:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|write_en_tx_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|clock_sel_s1_translator|av_readdata_pre ;wire [3:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [3:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_018|src_payload ;wire [31:0] \u0|timecode_rx|readdata ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used ;wire [3:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter ;wire [5:0] \A_SPW_TOP|SPW|RX|counter_neg ;wire [128:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|saved_grant ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used ;wire [7:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_009|arb|top_priority_reg ;wire [3:0] \A_SPW_TOP|SPW|RX|control_l_r ;wire [31:0] \u0|timecode_tx_ready|readdata ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rdata_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_019|saved_grant ;wire [11:0] \u0|hps_0|fpga_interfaces|h2f_AWID ;wire [1:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter ;wire [2:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_021|saved_grant ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rdata_fifo|mem_used ;wire [1:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter ;wire [31:0] \u0|mm_interconnect_0|led_pio_test_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_003|saved_grant ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|divclk ;wire [2:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_translator|wait_latency_counter ;wire [5:0] \A_SPW_TOP|tx_data|counter ;wire [152:0] \u0|mm_interconnect_0|rsp_mux_001|src_payload ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_006|saved_grant ;wire [3:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [128:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [2:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [5:0] \A_SPW_TOP|tx_data|rd_ptr ;wire [3:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [31:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|av_readdata_pre ;wire [0:0] \u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire ;wire [1:0] \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [31:0] \u0|mm_interconnect_0|write_en_tx_s1_translator|av_readdata_pre ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_data_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [31:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_WVALID ;wire [31:0] \u0|mm_interconnect_0|data_flag_rx_s1_translator|av_readdata_pre ;wire [31:0] \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre ;wire [7:0] \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [13:0] \m_x|info ;wire [31:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|av_readdata_pre ;wire [5:0] \A_SPW_TOP|rx_data|counter ;wire [29:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [2:0] \u0|hps_0|fpga_interfaces|h2f_AWSIZE ;wire [31:0] \u0|mm_interconnect_0|data_read_en_rx_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [9:0] \m_x|timecode ;wire [0:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|hps_0|fpga_interfaces|h2f_ARADDR ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|av_readdata_pre ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_011|src_data ;wire [31:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|av_readdata_pre ;wire [128:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|clock_sel_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|mm_interconnect_0|link_start_s1_translator|av_readdata_pre ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_014|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [3:0] \A_SPW_TOP|SPW|TX|global_counter_transfer ;wire [8:0] \A_SPW_TOP|tx_data|data_out ;wire [31:0] \u0|mm_interconnect_0|link_disable_s1_translator|av_readdata_pre ;wire [8:0] \A_SPW_TOP|SPW|TX|txdata_flagctrl_tx_last ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [13:0] \A_SPW_TOP|SPW|TX|timecode_s ;wire [0:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count ;wire [1:0] \u0|mm_interconnect_0|led_pio_test_s1_agent_rdata_fifo|mem_used ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_RREADY ;wire [128:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_009|src_data ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_009|src_payload ;wire [6:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_addr ;wire [1:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_008|src_data ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [31:0] \u0|fifo_full_tx_status|readdata ;wire [7:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_008|src_payload ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_015|saved_grant ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [0:0] \u0|hps_0|fpga_interfaces|h2f_BREADY ;wire [6:0] \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_007|src_data ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_007|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|data_flag_rx|readdata ;wire [128:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux|src_data ;wire [7:0] \u0|timecode_tx_data|data_out ;wire [7:0] \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_004|src_data ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_004|src_payload ;wire [6:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|saved_grant ;wire [152:0] \u0|mm_interconnect_0|cmd_mux|src_payload ;wire [6:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [2:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [1:0] \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter ;wire [31:0] \u0|timecode_tx_data|readdata ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [21:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [1:0] \u0|mm_interconnect_0|data_flag_rx_s1_agent_rsp_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [128:0] \u0|mm_interconnect_0|data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [1:0] \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used ;wire [6:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_018|src_data ;wire [1:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux|arb|top_priority_reg ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [31:0] \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [0:0] \u0|mm_interconnect_0|clock_sel_s1_translator|read_latency_shift_reg ;wire [128:0] \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [6:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_014|src_data ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_010|src_data ;wire [2:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [31:0] \u0|mm_interconnect_0|timecode_rx_s1_translator|av_readdata_pre ;wire [6:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [128:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg ;wire [152:0] \u0|mm_interconnect_0|cmd_mux_011|src_payload ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg ;wire [1:0] \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg ;wire [29:0] \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [31:0] \u0|fsm_info|readdata ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg ;wire [31:0] \u0|counter_rx_fifo|readdata ;wire [1:0] \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter ;wire [1:0] \u0|mm_interconnect_0|cmd_mux_001|saved_grant ;wire [8:0] \u0|write_data_fifo_tx|data_out ;wire [1:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used ;wire [128:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg ;wire [29:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [2:0] \u0|clock_sel|data_out ;wire [31:0] \u0|data_info|readdata ;wire [29:0] \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [128:0] \u0|mm_interconnect_0|cmd_mux_015|src_data ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|led_pio_test|readdata ;wire [29:0] \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly ;wire [1:0] \u0|mm_interconnect_0|link_start_s1_agent_rdata_fifo|mem_used ;wire [31:0] \u0|fifo_full_rx_status|readdata ;wire [31:0] \u0|fifo_empty_rx_status|readdata ;wire [29:0] \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [31:0] \u0|fifo_empty_tx_status|readdata ;wire [6:0] \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [9:0] \m_x|dta_timec_p ;wire [3:0] \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg ;wire [29:0] \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [6:0] \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [29:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [128:0] \u0|mm_interconnect_0|rsp_mux|src_data ;wire [29:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [8:0] \A_SPW_TOP|rx_data|data_out ;wire [8:0] \u0|data_flag_rx|read_mux_out ;wire [29:0] \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg ;wire [29:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg ;wire [6:0] \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg ;wire [9:0] \A_SPW_TOP|SPW|RX|timecode ;wire [31:0] \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ;wire [29:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ;wire [1:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ;wire [11:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ;wire [3:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ;wire [2:0] \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ;wire [127:0] \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ;wire [15:0] \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ;wire [7:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ;wire [8:0] \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ;assign \u0|hps_0|fpga_interfaces|tpiu~trace_data = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [0];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA1 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [1];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA2 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [2];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA3 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [3];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA4 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [4];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA5 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [5];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA6 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [6];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA7 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [7];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA8 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [8];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA9 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [9];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA10 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [10];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA11 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [11];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA12 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [12];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA13 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [13];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA14 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [14];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA15 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [15];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA16 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [16];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA17 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [17];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA18 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [18];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA19 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [19];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA20 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [20];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA21 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [21];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA22 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [22];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA23 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [23];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA24 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [24];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA25 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [25];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA26 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [26];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA27 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [27];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA28 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [28];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA29 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [29];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA30 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [30];assign \u0|hps_0|fpga_interfaces|tpiu~O_TRACE_DATA31 = \u0|hps_0|fpga_interfaces|tpiu_TRACE_DATA_bus [31];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_10 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [0];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_11 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [1];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_12 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [2];assign \u0|hps_0|fpga_interfaces|f2sdram~O_BONDING_OUT_13 = \u0|hps_0|fpga_interfaces|f2sdram_BONDING_OUT_1_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [20] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [20];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [21] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [21];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [22] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [22];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [23] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [23];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [24] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [24];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [25] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [25];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [26] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [26];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [27] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [27];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [28] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [28];assign \u0|hps_0|fpga_interfaces|h2f_ARADDR [29] = \u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus [29];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_ARID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_ARID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_ARID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_ARID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_ARID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_ARID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_ARID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_ARLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [12] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [12];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [13] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [13];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [14] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [14];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [15] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [15];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [16] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [16];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [17] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [17];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [18] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [18];assign \u0|hps_0|fpga_interfaces|h2f_AWADDR [19] = \u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus [19];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWBURST [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWID [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWID [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWID [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWID [4] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_AWID [5] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_AWID [6] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_AWID [7] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_AWID [8] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_AWID [9] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [9];assign \u0|hps_0|fpga_interfaces|h2f_AWID [10] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [10];assign \u0|hps_0|fpga_interfaces|h2f_AWID [11] = \u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus [11];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_AWLEN [3] = \u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [0] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] = \u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [3];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [4] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [4];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [5] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [5];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [6] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [6];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [7] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [7];assign \u0|hps_0|fpga_interfaces|h2f_WDATA [8] = \u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus [8];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [0];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [1];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [2];assign \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] = \u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [0];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [1];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [2];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [3];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [4];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [5];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [6];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus [7];assign \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [3] = \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus [3];// Location: IOOBUF_X65_Y0_N36cyclonev_io_obuf \dout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(dout_a),.obar(\dout_a(n) ));// synopsys translate_offdefparam \dout_a~output .bus_hold = "false";defparam \dout_a~output .open_drain_output = "false";defparam \dout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X53_Y0_N36cyclonev_io_obuf \sout_a~output (.i(\A_SPW_TOP|SPW|TX|tx_sout_e~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(sout_a),.obar(\sout_a(n) ));// synopsys translate_offdefparam \sout_a~output .bus_hold = "false";defparam \sout_a~output .open_drain_output = "false";defparam \sout_a~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y10_N96cyclonev_io_obuf \LED[5]~output (.i(\db_system_spwulight_b|PB_down~q ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[5]),.obar());// synopsys translate_offdefparam \LED[5]~output .bus_hold = "false";defparam \LED[5]~output .open_drain_output = "false";defparam \LED[5]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N56cyclonev_io_obuf \LED[7]~output (.i(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[7]),.obar());// synopsys translate_offdefparam \LED[7]~output .bus_hold = "false";defparam \LED[7]~output .open_drain_output = "false";defparam \LED[7]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N22cyclonev_io_obuf \LED[0]~output (.i(\u0|led_pio_test|data_out [0]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[0]),.obar());// synopsys translate_offdefparam \LED[0]~output .bus_hold = "false";defparam \LED[0]~output .open_drain_output = "false";defparam \LED[0]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N39cyclonev_io_obuf \LED[1]~output (.i(\u0|led_pio_test|data_out [1]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[1]),.obar());// synopsys translate_offdefparam \LED[1]~output .bus_hold = "false";defparam \LED[1]~output .open_drain_output = "false";defparam \LED[1]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N5cyclonev_io_obuf \LED[2]~output (.i(\u0|led_pio_test|data_out [2]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[2]),.obar());// synopsys translate_offdefparam \LED[2]~output .bus_hold = "false";defparam \LED[2]~output .open_drain_output = "false";defparam \LED[2]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y13_N22cyclonev_io_obuf \LED[3]~output (.i(\u0|led_pio_test|data_out [3]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[3]),.obar());// synopsys translate_offdefparam \LED[3]~output .bus_hold = "false";defparam \LED[3]~output .open_drain_output = "false";defparam \LED[3]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y10_N79cyclonev_io_obuf \LED[4]~output (.i(\u0|led_pio_test|data_out [4]),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[4]),.obar());// synopsys translate_offdefparam \LED[4]~output .bus_hold = "false";defparam \LED[4]~output .open_drain_output = "false";defparam \LED[4]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOOBUF_X68_Y12_N5cyclonev_io_obuf \LED[6]~output (.i(gnd),.oe(vcc),.dynamicterminationcontrol(gnd),.seriesterminationcontrol(16'b0000000000000000),.parallelterminationcontrol(16'b0000000000000000),.devoe(devoe),.o(LED[6]),.obar());// synopsys translate_offdefparam \LED[6]~output .bus_hold = "false";defparam \LED[6]~output .open_drain_output = "false";defparam \LED[6]~output .shift_series_termination_control = "false";// synopsys translate_on// Location: IOIBUF_X38_Y0_N1cyclonev_io_ibuf \FPGA_CLK1_50~input (.i(FPGA_CLK1_50),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\FPGA_CLK1_50~input_o ));// synopsys translate_offdefparam \FPGA_CLK1_50~input .bus_hold = "false";defparam \FPGA_CLK1_50~input .simulate_z_as = "z";// synopsys translate_on// Location: PLLREFCLKSELECT_X68_Y7_N0cyclonev_pll_refclk_select \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT (.adjpllin(gnd),.cclk(gnd),.coreclkin(gnd),.extswitch(gnd),.iqtxrxclkin(gnd),.plliqclkin(gnd),.rxiqclkin(gnd),.clkin({gnd,gnd,gnd,\FPGA_CLK1_50~input_o }),.refiqclk(2'b00),.clk0bad(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|clk0bad ),.clk1bad(),.clkout(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.extswitchbuf(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.pllclksel());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_auto_clk_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_edge = "both_edges";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_loss_sw_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clk_sw_dly = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_0_src = "clk_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_clkin_1_src = "clk_1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_manu_clk_sw_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT .pll_sw_refclk_src = "clk_0";// synopsys translate_on// Location: CLKCTRL_G5cyclonev_clkena \FPGA_CLK1_50~inputCLKENA0 (.inclk(\FPGA_CLK1_50~input_o ),.ena(vcc),.outclk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \FPGA_CLK1_50~inputCLKENA0 .clock_type = "global clock";defparam \FPGA_CLK1_50~inputCLKENA0 .disable_mode = "low";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_mode = "always enabled";defparam \FPGA_CLK1_50~inputCLKENA0 .ena_register_power_up = "high";defparam \FPGA_CLK1_50~inputCLKENA0 .test_syn = "high";// synopsys translate_on// Location: IOIBUF_X46_Y0_N52cyclonev_io_ibuf \KEY[1]~input (.i(KEY[1]),.ibar(gnd),.dynamicterminationcontrol(gnd),.o(\KEY[1]~input_o ));// synopsys translate_offdefparam \KEY[1]~input .bus_hold = "false";defparam \KEY[1]~input .simulate_z_as = "z";// synopsys translate_on// Location: MLABCELL_X47_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|aux_pb~0 (// Equation(s):// \db_system_spwulight_b|aux_pb~0_combout = !\KEY[1]~input_o.dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|aux_pb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb~0 .extended_lut = "off";defparam \db_system_spwulight_b|aux_pb~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \db_system_spwulight_b|aux_pb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|Add0~61 (// Equation(s):// \db_system_spwulight_b|Add0~61_sumout = SUM(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC ))// \db_system_spwulight_b|Add0~62 = CARRY(( \db_system_spwulight_b|counter [0] ) + ( VCC ) + ( !VCC )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~61_sumout ),.cout(\db_system_spwulight_b|Add0~62 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~61 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~61 .lut_mask = 64'h00000000000000FF;defparam \db_system_spwulight_b|Add0~61 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|counter~16 (// Equation(s):// \db_system_spwulight_b|counter~16_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~61_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~61_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~16_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~16 .extended_lut = "off";defparam \db_system_spwulight_b|counter~16 .lut_mask = 64'h00AA00AA00AA00AA;defparam \db_system_spwulight_b|counter~16 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~0 (// Equation(s):// \db_system_spwulight_b|LessThan0~0_combout = ( !\db_system_spwulight_b|counter [9] & ( (!\db_system_spwulight_b|counter [13] & (!\db_system_spwulight_b|counter [11] & (!\db_system_spwulight_b|counter [10] & !\db_system_spwulight_b|counter [12]))) ) ).dataa(!\db_system_spwulight_b|counter [13]),.datab(!\db_system_spwulight_b|counter [11]),.datac(!\db_system_spwulight_b|counter [10]),.datad(!\db_system_spwulight_b|counter [12]),.datae(gnd),.dataf(!\db_system_spwulight_b|counter [9]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~0 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~0 .lut_mask = 64'h8000800000000000;defparam \db_system_spwulight_b|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N6cyclonev_lcell_comb \db_system_spwulight_b|LessThan0~1 (// Equation(s):// \db_system_spwulight_b|LessThan0~1_combout = ( \db_system_spwulight_b|counter [7] & ( (\db_system_spwulight_b|counter [8] & (((\db_system_spwulight_b|counter [4]) # (\db_system_spwulight_b|counter [5])) # (\db_system_spwulight_b|counter [6]))) ) ).dataa(!\db_system_spwulight_b|counter [6]),.datab(!\db_system_spwulight_b|counter [5]),.datac(!\db_system_spwulight_b|counter [4]),.datad(!\db_system_spwulight_b|counter [8]),.datae(gnd),.dataf(!\db_system_spwulight_b|counter [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|LessThan0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|LessThan0~1 .extended_lut = "off";defparam \db_system_spwulight_b|LessThan0~1 .lut_mask = 64'h00000000007F007F;defparam \db_system_spwulight_b|LessThan0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N21cyclonev_lcell_comb \db_system_spwulight_b|counter[13]~1 (// Equation(s):// \db_system_spwulight_b|counter[13]~1_combout = ( \db_system_spwulight_b|LessThan0~1_combout & ( \KEY[1]~input_o ) ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( ((!\db_system_spwulight_b|counter [15] &// (\db_system_spwulight_b|LessThan0~0_combout & !\db_system_spwulight_b|counter [14]))) # (\KEY[1]~input_o ) ) ).dataa(!\db_system_spwulight_b|counter [15]),.datab(!\db_system_spwulight_b|LessThan0~0_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [14]),.datae(gnd),.dataf(!\db_system_spwulight_b|LessThan0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter[13]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter[13]~1 .extended_lut = "off";defparam \db_system_spwulight_b|counter[13]~1 .lut_mask = 64'h2F0F2F0F0F0F0F0F;defparam \db_system_spwulight_b|counter[13]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N59dffeas \db_system_spwulight_b|counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~16_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [0]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[0] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|Add0~57 (// Equation(s):// \db_system_spwulight_b|Add0~57_sumout = SUM(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 ))// \db_system_spwulight_b|Add0~58 = CARRY(( \db_system_spwulight_b|counter [1] ) + ( GND ) + ( \db_system_spwulight_b|Add0~62 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~62 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~57_sumout ),.cout(\db_system_spwulight_b|Add0~58 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~57 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~57 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~57 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N54cyclonev_lcell_comb \db_system_spwulight_b|counter~15 (// Equation(s):// \db_system_spwulight_b|counter~15_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~57_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~57_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~15 .extended_lut = "off";defparam \db_system_spwulight_b|counter~15 .lut_mask = 64'h0A0A0A0A0A0A0A0A;defparam \db_system_spwulight_b|counter~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N56dffeas \db_system_spwulight_b|counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~15_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [1]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[1] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N6cyclonev_lcell_comb \db_system_spwulight_b|Add0~53 (// Equation(s):// \db_system_spwulight_b|Add0~53_sumout = SUM(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 ))// \db_system_spwulight_b|Add0~54 = CARRY(( \db_system_spwulight_b|counter [2] ) + ( GND ) + ( \db_system_spwulight_b|Add0~58 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [2]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~58 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~53_sumout ),.cout(\db_system_spwulight_b|Add0~54 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~53 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~53 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~53 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N51cyclonev_lcell_comb \db_system_spwulight_b|counter~14 (// Equation(s):// \db_system_spwulight_b|counter~14_combout = ( \db_system_spwulight_b|Add0~53_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~53_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~14 .extended_lut = "off";defparam \db_system_spwulight_b|counter~14 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N53dffeas \db_system_spwulight_b|counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~14_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [2]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[2] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|Add0~49 (// Equation(s):// \db_system_spwulight_b|Add0~49_sumout = SUM(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 ))// \db_system_spwulight_b|Add0~50 = CARRY(( \db_system_spwulight_b|counter [3] ) + ( GND ) + ( \db_system_spwulight_b|Add0~54 )).dataa(!\db_system_spwulight_b|counter [3]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~54 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~49_sumout ),.cout(\db_system_spwulight_b|Add0~50 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~49 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~49 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~49 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X46_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~13 (// Equation(s):// \db_system_spwulight_b|counter~13_combout = ( \db_system_spwulight_b|Add0~49_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~49_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~13 .extended_lut = "off";defparam \db_system_spwulight_b|counter~13 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X46_Y1_N50dffeas \db_system_spwulight_b|counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~13_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [3]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[3] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N12cyclonev_lcell_comb \db_system_spwulight_b|Add0~37 (// Equation(s):// \db_system_spwulight_b|Add0~37_sumout = SUM(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 ))// \db_system_spwulight_b|Add0~38 = CARRY(( \db_system_spwulight_b|counter [4] ) + ( GND ) + ( \db_system_spwulight_b|Add0~50 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [4]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~50 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~37_sumout ),.cout(\db_system_spwulight_b|Add0~38 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~37 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~37 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~37 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N3cyclonev_lcell_comb \db_system_spwulight_b|counter~10 (// Equation(s):// \db_system_spwulight_b|counter~10_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~37_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~37_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~10 .extended_lut = "off";defparam \db_system_spwulight_b|counter~10 .lut_mask = 64'h00AA00AA00AA00AA;defparam \db_system_spwulight_b|counter~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N5dffeas \db_system_spwulight_b|counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~10_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [4]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[4] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N15cyclonev_lcell_comb \db_system_spwulight_b|Add0~41 (// Equation(s):// \db_system_spwulight_b|Add0~41_sumout = SUM(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 ))// \db_system_spwulight_b|Add0~42 = CARRY(( \db_system_spwulight_b|counter [5] ) + ( GND ) + ( \db_system_spwulight_b|Add0~38 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [5]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~38 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~41_sumout ),.cout(\db_system_spwulight_b|Add0~42 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~41 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~41 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~41 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N57cyclonev_lcell_comb \db_system_spwulight_b|counter~11 (// Equation(s):// \db_system_spwulight_b|counter~11_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~41_sumout ) ).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~41_sumout ),.datad(gnd),.datae(gnd),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~11 .extended_lut = "off";defparam \db_system_spwulight_b|counter~11 .lut_mask = 64'h0F0F0F0F00000000;defparam \db_system_spwulight_b|counter~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N59dffeas \db_system_spwulight_b|counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~11_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [5]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[5] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|Add0~45 (// Equation(s):// \db_system_spwulight_b|Add0~45_sumout = SUM(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 ))// \db_system_spwulight_b|Add0~46 = CARRY(( \db_system_spwulight_b|counter [6] ) + ( GND ) + ( \db_system_spwulight_b|Add0~42 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [6]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~42 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~45_sumout ),.cout(\db_system_spwulight_b|Add0~46 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~45 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~45 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~45 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N51cyclonev_lcell_comb \db_system_spwulight_b|counter~12 (// Equation(s):// \db_system_spwulight_b|counter~12_combout = ( \db_system_spwulight_b|Add0~45_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~45_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~12 .extended_lut = "off";defparam \db_system_spwulight_b|counter~12 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~12 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N53dffeas \db_system_spwulight_b|counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~12_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [6]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[6] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N21cyclonev_lcell_comb \db_system_spwulight_b|Add0~29 (// Equation(s):// \db_system_spwulight_b|Add0~29_sumout = SUM(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 ))// \db_system_spwulight_b|Add0~30 = CARRY(( \db_system_spwulight_b|counter [7] ) + ( GND ) + ( \db_system_spwulight_b|Add0~46 )).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|counter [7]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~46 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~29_sumout ),.cout(\db_system_spwulight_b|Add0~30 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~29 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~29 .lut_mask = 64'h0000FFFF000000FF;defparam \db_system_spwulight_b|Add0~29 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N9cyclonev_lcell_comb \db_system_spwulight_b|counter~8 (// Equation(s):// \db_system_spwulight_b|counter~8_combout = ( !\KEY[1]~input_o & ( \db_system_spwulight_b|Add0~29_sumout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~29_sumout ),.datae(gnd),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~8 .extended_lut = "off";defparam \db_system_spwulight_b|counter~8 .lut_mask = 64'h00FF00FF00000000;defparam \db_system_spwulight_b|counter~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N11dffeas \db_system_spwulight_b|counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~8_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [7]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[7] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N24cyclonev_lcell_comb \db_system_spwulight_b|Add0~33 (// Equation(s):// \db_system_spwulight_b|Add0~33_sumout = SUM(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 ))// \db_system_spwulight_b|Add0~34 = CARRY(( \db_system_spwulight_b|counter [8] ) + ( GND ) + ( \db_system_spwulight_b|Add0~30 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [8]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~30 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~33_sumout ),.cout(\db_system_spwulight_b|Add0~34 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~33 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~33 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~33 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N0cyclonev_lcell_comb \db_system_spwulight_b|counter~9 (// Equation(s):// \db_system_spwulight_b|counter~9_combout = ( \db_system_spwulight_b|Add0~33_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~33_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~9 .extended_lut = "off";defparam \db_system_spwulight_b|counter~9 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N2dffeas \db_system_spwulight_b|counter[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~9_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [8]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[8] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|Add0~9 (// Equation(s):// \db_system_spwulight_b|Add0~9_sumout = SUM(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 ))// \db_system_spwulight_b|Add0~10 = CARRY(( \db_system_spwulight_b|counter [9] ) + ( GND ) + ( \db_system_spwulight_b|Add0~34 )).dataa(!\db_system_spwulight_b|counter [9]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~34 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~9_sumout ),.cout(\db_system_spwulight_b|Add0~10 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~9 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~9 .lut_mask = 64'h0000FFFF00005555;defparam \db_system_spwulight_b|Add0~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|counter~3 (// Equation(s):// \db_system_spwulight_b|counter~3_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~9_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(!\db_system_spwulight_b|Add0~9_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~3 .extended_lut = "off";defparam \db_system_spwulight_b|counter~3 .lut_mask = 64'h0A0A0A0A0A0A0A0A;defparam \db_system_spwulight_b|counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N32dffeas \db_system_spwulight_b|counter[9] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~3_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [9]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[9] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N30cyclonev_lcell_comb \db_system_spwulight_b|Add0~13 (// Equation(s):// \db_system_spwulight_b|Add0~13_sumout = SUM(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 ))// \db_system_spwulight_b|Add0~14 = CARRY(( \db_system_spwulight_b|counter [10] ) + ( GND ) + ( \db_system_spwulight_b|Add0~10 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [10]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~10 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~13_sumout ),.cout(\db_system_spwulight_b|Add0~14 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~13 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~13 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~13 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|counter~4 (// Equation(s):// \db_system_spwulight_b|counter~4_combout = ( \db_system_spwulight_b|Add0~13_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~13_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~4 .extended_lut = "off";defparam \db_system_spwulight_b|counter~4 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N35dffeas \db_system_spwulight_b|counter[10] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~4_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [10]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[10] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[10] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N33cyclonev_lcell_comb \db_system_spwulight_b|Add0~17 (// Equation(s):// \db_system_spwulight_b|Add0~17_sumout = SUM(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 ))// \db_system_spwulight_b|Add0~18 = CARRY(( \db_system_spwulight_b|counter [11] ) + ( GND ) + ( \db_system_spwulight_b|Add0~14 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [11]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~14 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~17_sumout ),.cout(\db_system_spwulight_b|Add0~18 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~17 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~17 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~17 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|counter~5 (// Equation(s):// \db_system_spwulight_b|counter~5_combout = (!\KEY[1]~input_o & \db_system_spwulight_b|Add0~17_sumout ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(!\db_system_spwulight_b|Add0~17_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~5 .extended_lut = "off";defparam \db_system_spwulight_b|counter~5 .lut_mask = 64'h00AA00AA00AA00AA;defparam \db_system_spwulight_b|counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N44dffeas \db_system_spwulight_b|counter[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~5_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [11]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[11] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[11] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|Add0~21 (// Equation(s):// \db_system_spwulight_b|Add0~21_sumout = SUM(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 ))// \db_system_spwulight_b|Add0~22 = CARRY(( \db_system_spwulight_b|counter [12] ) + ( GND ) + ( \db_system_spwulight_b|Add0~18 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [12]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~18 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~21_sumout ),.cout(\db_system_spwulight_b|Add0~22 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~21 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~21 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~21 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|counter~6 (// Equation(s):// \db_system_spwulight_b|counter~6_combout = ( \db_system_spwulight_b|Add0~21_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~21_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~6 .extended_lut = "off";defparam \db_system_spwulight_b|counter~6 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N47dffeas \db_system_spwulight_b|counter[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~6_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [12]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[12] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N39cyclonev_lcell_comb \db_system_spwulight_b|Add0~25 (// Equation(s):// \db_system_spwulight_b|Add0~25_sumout = SUM(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 ))// \db_system_spwulight_b|Add0~26 = CARRY(( \db_system_spwulight_b|counter [13] ) + ( GND ) + ( \db_system_spwulight_b|Add0~22 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [13]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~22 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~25_sumout ),.cout(\db_system_spwulight_b|Add0~26 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~25 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~25 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~25 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N48cyclonev_lcell_comb \db_system_spwulight_b|counter~7 (// Equation(s):// \db_system_spwulight_b|counter~7_combout = ( \db_system_spwulight_b|Add0~25_sumout & ( !\KEY[1]~input_o ) ).dataa(!\KEY[1]~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~25_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~7 .extended_lut = "off";defparam \db_system_spwulight_b|counter~7 .lut_mask = 64'h00000000AAAAAAAA;defparam \db_system_spwulight_b|counter~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N50dffeas \db_system_spwulight_b|counter[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~7_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [13]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[13] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N42cyclonev_lcell_comb \db_system_spwulight_b|Add0~1 (// Equation(s):// \db_system_spwulight_b|Add0~1_sumout = SUM(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 ))// \db_system_spwulight_b|Add0~2 = CARRY(( \db_system_spwulight_b|counter [14] ) + ( GND ) + ( \db_system_spwulight_b|Add0~26 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [14]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~26 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~1_sumout ),.cout(\db_system_spwulight_b|Add0~2 ),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~1 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~1 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N27cyclonev_lcell_comb \db_system_spwulight_b|counter~0 (// Equation(s):// \db_system_spwulight_b|counter~0_combout = ( \db_system_spwulight_b|Add0~1_sumout & ( !\KEY[1]~input_o ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\db_system_spwulight_b|Add0~1_sumout ),.dataf(!\KEY[1]~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~0 .extended_lut = "off";defparam \db_system_spwulight_b|counter~0 .lut_mask = 64'h0000FFFF00000000;defparam \db_system_spwulight_b|counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N29dffeas \db_system_spwulight_b|counter[14] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [14]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[14] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[14] .power_up = "low";// synopsys translate_on// Location: LABCELL_X46_Y1_N45cyclonev_lcell_comb \db_system_spwulight_b|Add0~5 (// Equation(s):// \db_system_spwulight_b|Add0~5_sumout = SUM(( \db_system_spwulight_b|counter [15] ) + ( GND ) + ( \db_system_spwulight_b|Add0~2 )).dataa(gnd),.datab(gnd),.datac(!\db_system_spwulight_b|counter [15]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\db_system_spwulight_b|Add0~2 ),.sharein(gnd),.combout(),.sumout(\db_system_spwulight_b|Add0~5_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|Add0~5 .extended_lut = "off";defparam \db_system_spwulight_b|Add0~5 .lut_mask = 64'h0000FFFF00000F0F;defparam \db_system_spwulight_b|Add0~5 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X47_Y1_N36cyclonev_lcell_comb \db_system_spwulight_b|counter~2 (// Equation(s):// \db_system_spwulight_b|counter~2_combout = ( \db_system_spwulight_b|Add0~5_sumout & ( !\KEY[1]~input_o ) ).dataa(gnd),.datab(gnd),.datac(!\KEY[1]~input_o ),.datad(gnd),.datae(gnd),.dataf(!\db_system_spwulight_b|Add0~5_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|counter~2 .extended_lut = "off";defparam \db_system_spwulight_b|counter~2 .lut_mask = 64'h00000000F0F0F0F0;defparam \db_system_spwulight_b|counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N38dffeas \db_system_spwulight_b|counter[15] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|counter~2_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|counter[13]~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|counter [15]),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|counter[15] .is_wysiwyg = "true";defparam \db_system_spwulight_b|counter[15] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X47_Y1_N18cyclonev_lcell_comb \db_system_spwulight_b|PB_down~0 (// Equation(s):// \db_system_spwulight_b|PB_down~0_combout = ( \db_system_spwulight_b|LessThan0~1_combout ) # ( !\db_system_spwulight_b|LessThan0~1_combout & ( ((!\db_system_spwulight_b|LessThan0~0_combout ) # ((\db_system_spwulight_b|counter [14]) # (\KEY[1]~input_o// ))) # (\db_system_spwulight_b|counter [15]) ) ).dataa(!\db_system_spwulight_b|counter [15]),.datab(!\db_system_spwulight_b|LessThan0~0_combout ),.datac(!\KEY[1]~input_o ),.datad(!\db_system_spwulight_b|counter [14]),.datae(gnd),.dataf(!\db_system_spwulight_b|LessThan0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\db_system_spwulight_b|PB_down~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \db_system_spwulight_b|PB_down~0 .extended_lut = "off";defparam \db_system_spwulight_b|PB_down~0 .lut_mask = 64'hDFFFDFFFFFFFFFFF;defparam \db_system_spwulight_b|PB_down~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X47_Y1_N14dffeas \db_system_spwulight_b|aux_pb (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\db_system_spwulight_b|aux_pb~0_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\db_system_spwulight_b|PB_down~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\db_system_spwulight_b|aux_pb~q ),.prn(vcc));// synopsys translate_offdefparam \db_system_spwulight_b|aux_pb .is_wysiwyg = "true";defparam \db_system_spwulight_b|aux_pb .power_up = "low";// synopsys translate_on// Location: FRACTIONALPLL_X68_Y1_N0cyclonev_fractional_pll \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll (.coreclkfb(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.ecnc1test(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_extswitchbuf_wire ),.ecnc2test(gnd),.fbclkfpll(gnd),.lvdsfbin(gnd),.nresync(!\db_system_spwulight_b|aux_pb~q ),.pfden(vcc),.refclkin(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|refclk_select_clkout_wire ),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdonein(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.zdb(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fbclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fboutclk_wire [0]),.fblvdsout(),.lock(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.mcntout(),.plniotribuf(),.shiftdoneout(),.tclk(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.mhi(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_MHI_bus ),.vcoph(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_VCOPH_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .dsm_accumulator_reset_value = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .forcelock = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .mimic_fbclk_type = "none";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .nreset_invert = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_atb = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_bwctrl = 4000;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cmp_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_comp = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_cp_current = 10;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ctrl_override_setting = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_dither = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_out_sel = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_dsm_reset = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ecn_test_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_enable = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_1 = "glb";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fbclk_mux_2 = "m_cnt";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_carry_out = 32;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_division_string = "1";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_fractional_value_ready = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lf_testen = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_cfg = 25;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_lock_fltr_test = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_hi_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_lo_div = 4;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_m_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_bypass_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_hi_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_lo_div = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_n_cnt_odd_div_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ref_buf_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_reg_boost = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_regulator_bypass = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_ripplecap_ctrl = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_slf_rst = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_mux_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_tclk_sel = "n_src";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_test_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testdn_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_testup_enable = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_unlock_fltr_cfg = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_div = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph0_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph1_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph2_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph3_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph4_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph5_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph6_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vco_ph7_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .pll_vctrl_test_voltage = 750;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .reference_clock_frequency = "100.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd0g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_atb = "disable";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccd1g_output = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccm1g_tap = 2;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vccr_pd = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .vcodiv_override = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll .fractional_pll_index = 0;// synopsys translate_on// Location: PLLRECONFIG_X68_Y5_N0cyclonev_pll_reconfig \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG (.atpgmode(gnd),.clk(gnd),.cntnen(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.fpllcsrtest(gnd),.iocsrclkin(gnd),.iocsrdatain(gnd),.iocsren(gnd),.iocsrrstn(gnd),.mdiodis(vcc),.phaseen(gnd),.read(gnd),.rstn(vcc),.scanen(gnd),.sershiftload(vcc),.shiftdonei(gnd),.updn(gnd),.write(gnd),.addr(6'b000000),.byteen(2'b00),.cntsel(5'b00000),.din(16'b0000000000000000),.mhi({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll_mhi_bus [0]}),.blockselect(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|blockselect ),.iocsrdataout(),.iocsrenbuf(),.iocsrrstnbuf(),.phasedone(),.shift(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftenm(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_shiftenm_wire ),.up(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.dout(),.dprioout(),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG_SHIFTEN_bus ));// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|PLL_RECONFIG .fractional_pll_index = 0;// synopsys translate_on// Location: PLLOUTPUTCOUNTER_X68_Y3_N1cyclonev_pll_output_counter \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter (.cascadein(gnd),.nen0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|cntnen ),.shift0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shift ),.shiftdone0i(gnd),.shiften(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|shiften [3]),.tclk0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|tclk ),.up0(\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|pll_reconfig_up_wire ),.vco0ph({\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [7],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [6],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [5],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [4],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [3],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [2],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [1],\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|vcoph [0]}),.cascadeout(\u0|pll_0|altera_pll_i|cyclonev_pll|cascade_wire [0]),.divclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.shiftdone0o());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_coarse_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_fine_dly = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_in_src = "ph_mux_clk";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_ph_mux_prst = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .c_cnt_prst = 1;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .cnt_fpll_src = "fpll_0";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_bypass_en = "true";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_hi_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_lo_div = 256;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .dprio0_cnt_odd_div_even_duty_en = "false";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .duty_cycle = 50;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_clock_frequency = "400.0 mhz";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .phase_shift = "0 ps";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .fractional_pll_index = 0;defparam \u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter .output_counter_index = 3;// synopsys translate_on// Location: CLKCTRL_G11cyclonev_clkena \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 (.inclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk [0]),.ena(vcc),.outclk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .clock_type = "global clock";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .disable_mode = "low";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: LABCELL_X27_Y1_N12cyclonev_lcell_comb \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y1_N14dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y1_N41dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y1_N38dffeas \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: CLKCTRL_G6cyclonev_clkena \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 (.inclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.ena(vcc),.outclk(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .clock_type = "global clock";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .disable_mode = "low";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .ena_register_power_up = "high";defparam \u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X17_Y19_N8dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y19_N50dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h0000FFFFFCFC3030;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y19_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y32_N1dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y26_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N50dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y26_N59dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y28_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|src_payload [0] = ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] & ( (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WLAST [0] &// ( \u0|mm_interconnect_0|cmd_mux_009|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_009|saved_grant [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .lut_mask = 64'h555555555F5F5F5F;defparam \u0|mm_interconnect_0|cmd_mux_009|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N2dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y26_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2] $ (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) )// # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h00FF00FFCA3ACA3A;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N53dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y26_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))// ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))// ) ) ) # ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFB83074FC;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N38dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y26_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y26_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h02FE02FECE32CE32;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N31dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y26_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) )// ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & ( (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0030FFFCAA3055FC;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y26_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout & (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout &// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.datae(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hA000000000000000;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y26_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # ( !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout// & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h04EE04EE00AA00AA;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y26_N29dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y26_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout &// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ).dataa(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|link_disable_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0AAA0AAA02220222;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y28_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_009|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y28_N29dffeas \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_009|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_009|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y28_N30cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal15~1 (// Equation(s):// \u0|mm_interconnect_0|router|Equal15~1_combout = ( \u0|mm_interconnect_0|router|Equal15~0_combout & ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|router|Equal15~0_combout ),.dataf(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal15~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal15~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal15~1 .lut_mask = 64'h0000000000003333;defparam \u0|mm_interconnect_0|router|Equal15~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y26_N3cyclonev_lcell_comb \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder (// Equation(s):// \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .extended_lut = "off";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: HPSINTERFACECLOCKSRESETS_X32_Y50_N111cyclonev_hps_interface_clocks_resets \u0|hps_0|fpga_interfaces|clocks_resets (.f2h_cold_rst_req_n(vcc),.f2h_dbg_rst_req_n(vcc),.f2h_pending_rst_ack(vcc),.f2h_periph_ref_clk(gnd),.f2h_sdram_ref_clk(gnd),.f2h_warm_rst_req_n(vcc),.ptp_ref_clk(gnd),.h2f_cold_rst_n(\u0|hps_0|fpga_interfaces|clocks_resets~h2f_cold_rst_n ),.h2f_pending_rst_req_n(),.h2f_rst_n(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.h2f_user0_clk(),.h2f_user1_clk(),.h2f_user2_clk());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user0_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user1_clk_freq = 100;defparam \u0|hps_0|fpga_interfaces|clocks_resets .h2f_user2_clk_freq = 100;// synopsys translate_on// Location: CLKCTRL_G10cyclonev_clkena \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 (.inclk(\u0|hps_0|fpga_interfaces|h2f_rst_n [0]),.ena(vcc),.outclk(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.enaout());// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .clock_type = "global clock";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .disable_mode = "low";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_mode = "always enabled";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .ena_register_power_up = "high";defparam \u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0 .test_syn = "high";// synopsys translate_on// Location: FF_X10_Y26_N5dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1]~feeder_combout ),.asdata(vcc),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y26_N1dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [1]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y27_N47dffeas \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain [0]),.clrn(\u0|hps_0|fpga_interfaces|h2f_rst_n[0]~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.prn(vcc));// synopsys translate_offdefparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .is_wysiwyg = "true";defparam \u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out .power_up = "low";// synopsys translate_on// Location: FF_X17_Y19_N14dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h51005100F300F300;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y24_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (// !\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y24_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y24_N50dffeas \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_014|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_014|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y24_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_014|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST// [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_014|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .lut_mask = 64'h000F000FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_014|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y20_N44dffeas \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y24_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_018|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_018|arb|top_priority_reg[0]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y24_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST// [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .lut_mask = 64'h000F000FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_018|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N50dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0].dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|pending_response_count[0]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y27_N51cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout = !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0].dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|pending_response_count[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y19_N8dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][130] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_018|src_payload [0] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_018|src_payload [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y20_N32dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: FF_X11_Y25_N11dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][109] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y28_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y28_N2dffeas \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: FF_X17_Y25_N32dffeas \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem~16_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_disable_s1_agent_rsp_fifo|mem[1][111] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y26_N56dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y21_N21cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y21_N23dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: FF_X13_Y19_N32dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y19_N19dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]// & \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFF0FFF0;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y19_N17dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y19_N23dffeas \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_018|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y19_N5dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q & ( (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q & (// (\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][69]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h550055FF550055FF;defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y19_N59dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_018|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout = ( !\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout & ( ((!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ) #// (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q )) # (\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][66]~q ),.datac(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][69]~q ),.datad(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][68]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|clock_sel_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .lut_mask = 64'hFF3FFF3F00000000;defparam \u0|mm_interconnect_0|rsp_demux_018|src1_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N56dffeas \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]) # (\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY// [0] & ( (!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .lut_mask = 64'h0A0A0A0A5F5F5F5F;defparam \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y21_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y21_N5dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y24_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & (// \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout// & ( (\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] & (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout// & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout// ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_014|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src14_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000050F0103050F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y19_N32dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_014|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .lut_mask = 64'h000000000FFF0FFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N29dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_014|saved_grant [0] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_014|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y20_N32dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y20_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h02570257AAFFAAFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0FFF0FFF0F0F0F0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N50dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout & ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|comb~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N47dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .lut_mask = 64'h00F000F000000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter// [0] $ (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N8dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout $ (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1])))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_write~combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h0015001500B700B7;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter// [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y20_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0] $ (((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout & ( !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1] & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q & \u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|waitrequest_reset_override~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|local_write~combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .lut_mask = 64'h0303210300000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y20_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|m0_read~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|cp_ready~4_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|nonposted_write_endofpacket~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h022202220AAA0AAA;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & (((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout )) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00F700F7FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N35dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|rsp_demux_014|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0707070707000700;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h1F1F1F1F00000000;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N47dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout = (!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout &// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]))))) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout $ (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]))).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h713F713F713F713F;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y19_N44dffeas \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rdata_fifo|mem_used [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_data_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .lut_mask = 64'hCC00CC0088008800;defparam \u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_014|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout = ( !\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_014|src0_valid~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_data_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_014|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .lut_mask = 64'hAAAAAAAA00000000;defparam \u0|mm_interconnect_0|rsp_demux_014|src1_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter// [0] & !\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|wait_latency_counter [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000030303030;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y21_N38dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y21_N2dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y21_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal7~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal7~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal7~0 .lut_mask = 64'h00FF00FF00000000;defparam \u0|mm_interconnect_0|router_001|Equal7~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal10~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal10~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|mm_interconnect_0|router_001|Equal7~0_combout &// (\u0|mm_interconnect_0|router_001|Equal2~0_combout & \u0|hps_0|fpga_interfaces|h2f_ARADDR [16]))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal10~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal10~0 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|router_001|Equal10~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y31_N20dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[20] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y29_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|router_001|Equal10~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|router_001|Equal10~0_combout & (// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [20]),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.dataf(!\u0|mm_interconnect_0|router_001|Equal10~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .lut_mask = 64'h0000000055550505;defparam \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout )))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h004C004C004C004C;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y21_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y21_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y21_N29dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y21_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h45BF45BF40BA40BA;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y21_N56dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))// ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h5404AEFE0404FEFE;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y21_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00000000C000C000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y21_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h04FE04FEAE54AE54;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y21_N26dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y21_N13dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h2020DFDF7520DF8A;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y21_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5513551355005500;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y21_N20dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ((\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00F000F001F301F3;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y21_N50dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y21_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hFF00FF0000000000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y21_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (// !\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hA0E00000E0E00000;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N57cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (// !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_BREADY [0] & ( !\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_010|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_010|arb|top_priority_reg[0]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h000A000AAAAAAAAA;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y12_N6cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~5 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~6 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~2 )).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .lut_mask = 64'h0000FFFF00003333;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y12_N9cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~13 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~14 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~6 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~6 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N18cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~13_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N20dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~4_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N12cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~17 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~18 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~14 )).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~14 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .lut_mask = 64'h0000FFFF00003333;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~17 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N12cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(!\R_400_to_2_5_10_100_200_300MHZ|Add1~17_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .lut_mask = 64'h0303030303030303;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N14dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~5_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N15cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~21 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~22 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~18 )).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~18 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .lut_mask = 64'h0000FFFF00005555;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~21 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N21cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~21_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N23dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~6_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N18cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~25 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~26 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~22 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~22 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~26 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~25 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N15cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~25_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N17dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~7_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N21cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~29 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~26 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~30 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~26 )).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~26 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .lut_mask = 64'h0000FFFF00005555;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~29 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N0cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(!\R_400_to_2_5_10_100_200_300MHZ|Add1~29_sumout ),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .lut_mask = 64'h0303030303030303;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N2dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~8_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N24cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~33 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~34 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [8] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~30 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~30 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~33 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N3cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~33_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N5dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~9_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N27cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~37 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~38 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~34 )).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~34 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .lut_mask = 64'h0000FFFF00005555;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~37 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N33cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout = (\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout & \R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(!\R_400_to_2_5_10_100_200_300MHZ|Add1~37_sumout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .lut_mask = 64'h0033003300330033;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N35dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~10_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N30cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~41 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~38 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~38 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~41 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N30cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~41_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .lut_mask = 64'h0000000033333333;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N32dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~11_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[10] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y12_N24cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10] ) ).dataa(gnd),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [10]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [9]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .lut_mask = 64'hCCCCCCCC00000000;defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y12_N0cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~9 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~10 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [0] ) + ( VCC ) + ( !VCC )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .lut_mask = 64'h0000000000000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N9cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~9_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .lut_mask = 64'h000000000F0F0F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N11dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~3_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y12_N54cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout = ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7] & ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3] & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5] &// (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4] & (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6] & !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]))) ) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [5]),.datab(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [4]),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [6]),.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [8]),.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [7]),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .lut_mask = 64'h8000000000000000;defparam \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N42cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2] &// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & \R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout )) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & (// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & (\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout & ((!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]) # (!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0])))) ) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datab(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .lut_mask = 64'h0000000003020202;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y12_N3cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|Add1~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout = SUM(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 ))// \R_400_to_2_5_10_100_200_300MHZ|Add1~2 = CARRY(( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] ) + ( GND ) + ( \R_400_to_2_5_10_100_200_300MHZ|Add1~10 )).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(\R_400_to_2_5_10_100_200_300MHZ|Add1~10 ),.sharein(gnd),.combout(),.sumout(\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),.cout(\R_400_to_2_5_10_100_200_300MHZ|Add1~2 ),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .lut_mask = 64'h0000FFFF00000F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y12_N57cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|Add1~1_sumout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .lut_mask = 64'h000000000F0F0F0F;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N59dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~1_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y12_N36cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout = ( \R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout & ( \R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\R_400_to_2_5_10_100_200_300MHZ|Add1~5_sumout ),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|counter_100[9]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .lut_mask = 64'h000000000000FFFF;defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y12_N38dffeas \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(\R_400_to_2_5_10_100_200_300MHZ|counter_100~2_combout ),.asdata(vcc),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|counter_100[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y12_N48cyclonev_lcell_comb \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 (// Equation(s):// \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout = ( \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock &// ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]))) ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( \R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & (// (\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock & ((!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]) # ((!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ) # (\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0])))) ) ) ) # (// \R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & ( !\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) ) ) # ( !\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1] & (// !\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout & ( \u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ) ) ).dataa(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [2]),.datab(!\u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|lock ),.datac(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_combout ),.datad(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [0]),.datae(!\R_400_to_2_5_10_100_200_300MHZ|counter_100 [1]),.dataf(!\R_400_to_2_5_10_100_200_300MHZ|LessThan16~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .extended_lut = "off";defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .lut_mask = 64'h3333333332333131;defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y11_N29dffeas \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i (.clk(\u0|pll_0|altera_pll_i|cyclonev_pll|divclk[0]~CLKENA0_outclk ),.d(gnd),.asdata(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~0_combout ),.clrn(vcc),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i~q ),.prn(vcc));// synopsys translate_offdefparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .is_wysiwyg = "true";defparam \R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i .power_up = "low";// synopsys translate_on// Location: IOIBUF_X51_Y0_N1cyclonev_io_ibuf \sin_a~input (.i(sin_a),.ibar(\sin_a(n) ),.dynamicterminationcontrol(gnd),.o(\sin_a~input_o ));// synopsys translate_offdefparam \sin_a~input .bus_hold = "false";defparam \sin_a~input .simulate_z_as = "z";// synopsys translate_on// Location: IOIBUF_X46_Y0_N1cyclonev_io_ibuf \din_a~input (.i(din_a),.ibar(\din_a(n) ),.dynamicterminationcontrol(gnd),.o(\din_a~input_o ));// synopsys translate_offdefparam \din_a~input .bus_hold = "false";defparam \din_a~input .simulate_z_as = "z";// synopsys translate_on// Location: LABCELL_X31_Y15_N39cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|always3~0 (// Equation(s):// \A_SPW_TOP|SPW|RX|always3~0_combout = LCELL(( \din_a~input_o & ( !\sin_a~input_o ) ) # ( !\din_a~input_o & ( \sin_a~input_o ) )).dataa(!\sin_a~input_o ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\din_a~input_o ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|always3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|always3~0 .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|always3~0 .lut_mask = 64'h55555555AAAAAAAA;defparam \A_SPW_TOP|SPW|RX|always3~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X35_Y15_N9cyclonev_lcell_comb \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder (// Equation(s):// \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\A_SPW_TOP|SPW|RX|counter_neg[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .extended_lut = "off";defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \A_SPW_TOP|SPW|RX|counter_neg[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y14_N33cyclonev_lcell_comb \m_x|counter_neg[0]~feeder (// Equation(s):// \m_x|counter_neg[0]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|counter_neg[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|counter_neg[0]~feeder .extended_lut = "off";defparam \m_x|counter_neg[0]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \m_x|counter_neg[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N6cyclonev_lcell_comb \m_x|Selector2~0 (// Equation(s):// \m_x|Selector2~0_combout = ( \m_x|counter_neg [0] & ( \m_x|counter_neg [2] & ( \m_x|counter_neg [4] ) ) ) # ( !\m_x|counter_neg [0] & ( \m_x|counter_neg [2] & ( \m_x|counter_neg [4] ) ) ) # ( \m_x|counter_neg [0] & ( !\m_x|counter_neg [2] & (// (!\m_x|counter_neg [1] & ((!\m_x|counter_neg [5] & ((\m_x|counter_neg [3]))) # (\m_x|counter_neg [5] & (\m_x|counter_neg [4])))) # (\m_x|counter_neg [1] & (\m_x|counter_neg [4])) ) ) ) # ( !\m_x|counter_neg [0] & ( !\m_x|counter_neg [2] & (// \m_x|counter_neg [4] ) ) ).dataa(!\m_x|counter_neg [1]),.datab(!\m_x|counter_neg [4]),.datac(!\m_x|counter_neg [3]),.datad(!\m_x|counter_neg [5]),.datae(!\m_x|counter_neg [0]),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector2~0 .extended_lut = "off";defparam \m_x|Selector2~0 .lut_mask = 64'h33331B3333333333;defparam \m_x|Selector2~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N44dffeas \m_x|counter_neg[4] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector2~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [4]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[4] .is_wysiwyg = "true";defparam \m_x|counter_neg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y14_N21cyclonev_lcell_comb \m_x|Selector1~0 (// Equation(s):// \m_x|Selector1~0_combout = ( \m_x|counter_neg [5] & ( \m_x|counter_neg [1] ) ) # ( \m_x|counter_neg [5] & ( !\m_x|counter_neg [1] & ( (((!\m_x|counter_neg [0]) # (\m_x|counter_neg [4])) # (\m_x|counter_neg [2])) # (\m_x|counter_neg [3]) ) ) ) # (// !\m_x|counter_neg [5] & ( !\m_x|counter_neg [1] & ( (!\m_x|counter_neg [3] & (!\m_x|counter_neg [2] & (\m_x|counter_neg [4] & \m_x|counter_neg [0]))) ) ) ).dataa(!\m_x|counter_neg [3]),.datab(!\m_x|counter_neg [2]),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|counter_neg [0]),.datae(!\m_x|counter_neg [5]),.dataf(!\m_x|counter_neg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector1~0 .extended_lut = "off";defparam \m_x|Selector1~0 .lut_mask = 64'h0008FF7F0000FFFF;defparam \m_x|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N59dffeas \m_x|counter_neg[5] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector1~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [5]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[5] .is_wysiwyg = "true";defparam \m_x|counter_neg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y14_N24cyclonev_lcell_comb \m_x|Selector4~0 (// Equation(s):// \m_x|Selector4~0_combout = ( !\m_x|counter_neg [4] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & !\m_x|counter_neg [3])) ) ).dataa(!\m_x|counter_neg [0]),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|counter_neg [3]),.datad(gnd),.datae(gnd),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector4~0 .extended_lut = "off";defparam \m_x|Selector4~0 .lut_mask = 64'h4040404000000000;defparam \m_x|Selector4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N42cyclonev_lcell_comb \m_x|Selector4~1 (// Equation(s):// \m_x|Selector4~1_combout = ( \m_x|counter_neg [1] & ( (\m_x|Selector4~0_combout ) # (\m_x|counter_neg [2]) ) ) # ( !\m_x|counter_neg [1] & ( (\m_x|counter_neg [2] & !\m_x|Selector4~0_combout ) ) ).dataa(gnd),.datab(!\m_x|counter_neg [2]),.datac(!\m_x|Selector4~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\m_x|counter_neg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector4~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector4~1 .extended_lut = "off";defparam \m_x|Selector4~1 .lut_mask = 64'h303030303F3F3F3F;defparam \m_x|Selector4~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N17dffeas \m_x|counter_neg[2] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector4~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[2] .is_wysiwyg = "true";defparam \m_x|counter_neg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y14_N3cyclonev_lcell_comb \m_x|WideOr7~0 (// Equation(s):// \m_x|WideOr7~0_combout = ( !\m_x|counter_neg [3] & ( \m_x|counter_neg [4] & ( (!\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & \m_x|counter_neg [0]))) ) ) ) # ( \m_x|counter_neg [3] & ( !\m_x|counter_neg [4] & (// (!\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & \m_x|counter_neg [0]))) ) ) ) # ( !\m_x|counter_neg [3] & ( !\m_x|counter_neg [4] & ( (!\m_x|counter_neg [1] & ((!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] $ (\m_x|counter_neg// [0]))) # (\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & \m_x|counter_neg [0])))) # (\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & (!\m_x|counter_neg [5] & \m_x|counter_neg [0]))) ) ) ).dataa(!\m_x|counter_neg [1]),.datab(!\m_x|counter_neg [2]),.datac(!\m_x|counter_neg [5]),.datad(!\m_x|counter_neg [0]),.datae(!\m_x|counter_neg [3]),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|WideOr7~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|WideOr7~0 .extended_lut = "off";defparam \m_x|WideOr7~0 .lut_mask = 64'h8068008000800000;defparam \m_x|WideOr7~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y14_N35dffeas \m_x|counter_neg[0] (.clk(!\m_x|always3~0_combout ),.d(\m_x|counter_neg[0]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|WideOr7~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [0]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[0] .is_wysiwyg = "true";defparam \m_x|counter_neg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y14_N54cyclonev_lcell_comb \m_x|Selector3~0 (// Equation(s):// \m_x|Selector3~0_combout = ( !\m_x|counter_neg [4] & ( (\m_x|counter_neg [0] & !\m_x|counter_neg [5]) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|counter_neg [0]),.datad(!\m_x|counter_neg [5]),.datae(gnd),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector3~0 .extended_lut = "off";defparam \m_x|Selector3~0 .lut_mask = 64'h0F000F0000000000;defparam \m_x|Selector3~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N13dffeas \m_x|control_bit_found (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_bit_found~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|control_bit_found .is_wysiwyg = "true";defparam \m_x|control_bit_found .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y14_N57cyclonev_lcell_comb \m_x|Selector0~1 (// Equation(s):// \m_x|Selector0~1_combout = ( \m_x|control_bit_found~q & ( (!\m_x|is_control~q & (\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & !\m_x|counter_neg [5]))) # (\m_x|is_control~q & ((!\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & !\m_x|counter_neg [5]))// # (\m_x|counter_neg [1] & ((!\m_x|counter_neg [2]) # (!\m_x|counter_neg [5]))))) ) ) # ( !\m_x|control_bit_found~q & ( (\m_x|is_control~q & ((!\m_x|counter_neg [1] & (!\m_x|counter_neg [2] & !\m_x|counter_neg [5])) # (\m_x|counter_neg [1] &// (!\m_x|counter_neg [2] $ (!\m_x|counter_neg [5]))))) ) ).dataa(!\m_x|is_control~q ),.datab(!\m_x|counter_neg [1]),.datac(!\m_x|counter_neg [2]),.datad(!\m_x|counter_neg [5]),.datae(gnd),.dataf(!\m_x|control_bit_found~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~1 .extended_lut = "off";defparam \m_x|Selector0~1 .lut_mask = 64'h4110411071107110;defparam \m_x|Selector0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N27cyclonev_lcell_comb \m_x|Selector0~0 (// Equation(s):// \m_x|Selector0~0_combout = ( \m_x|counter_neg [2] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [5] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [3]))) ) ) # ( !\m_x|counter_neg [2] & ( (\m_x|counter_neg [0] & (!\m_x|counter_neg [4] & !\m_x|counter_neg// [3])) ) ).dataa(!\m_x|counter_neg [0]),.datab(!\m_x|counter_neg [5]),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|counter_neg [3]),.datae(gnd),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~0 .extended_lut = "off";defparam \m_x|Selector0~0 .lut_mask = 64'h5000500040004000;defparam \m_x|Selector0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N30cyclonev_lcell_comb \m_x|Equal1~0 (// Equation(s):// \m_x|Equal1~0_combout = ( !\m_x|counter_neg [4] & ( (\m_x|counter_neg [0] & !\m_x|counter_neg [3]) ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|counter_neg [0]),.datad(!\m_x|counter_neg [3]),.datae(gnd),.dataf(!\m_x|counter_neg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Equal1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Equal1~0 .extended_lut = "off";defparam \m_x|Equal1~0 .lut_mask = 64'h0F000F0000000000;defparam \m_x|Equal1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N54cyclonev_lcell_comb \m_x|Selector0~2 (// Equation(s):// \m_x|Selector0~2_combout = ( \m_x|Equal1~0_combout & ( (!\m_x|Selector0~0_combout & (\m_x|is_control~q )) # (\m_x|Selector0~0_combout & ((\m_x|Selector0~1_combout ))) ) ) # ( !\m_x|Equal1~0_combout & ( (\m_x|is_control~q & !\m_x|Selector0~0_combout// ) ) ).dataa(!\m_x|is_control~q ),.datab(gnd),.datac(!\m_x|Selector0~1_combout ),.datad(!\m_x|Selector0~0_combout ),.datae(gnd),.dataf(!\m_x|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector0~2 .extended_lut = "off";defparam \m_x|Selector0~2 .lut_mask = 64'h55005500550F550F;defparam \m_x|Selector0~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N56dffeas \m_x|is_control (.clk(!\m_x|always3~0_combout ),.d(\m_x|Selector0~2_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|is_control~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|is_control .is_wysiwyg = "true";defparam \m_x|is_control .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y14_N57cyclonev_lcell_comb \m_x|Selector3~1 (// Equation(s):// \m_x|Selector3~1_combout = ( \m_x|counter_neg [2] & ( ((\m_x|Selector3~0_combout & (!\m_x|is_control~q & !\m_x|counter_neg [1]))) # (\m_x|counter_neg [3]) ) ) # ( !\m_x|counter_neg [2] & ( (\m_x|counter_neg [3] & ((!\m_x|Selector3~0_combout ) #// (\m_x|counter_neg [1]))) ) ).dataa(!\m_x|Selector3~0_combout ),.datab(!\m_x|is_control~q ),.datac(!\m_x|counter_neg [1]),.datad(!\m_x|counter_neg [3]),.datae(gnd),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector3~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector3~1 .extended_lut = "off";defparam \m_x|Selector3~1 .lut_mask = 64'h00AF00AF40FF40FF;defparam \m_x|Selector3~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N29dffeas \m_x|counter_neg[3] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector3~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[3] .is_wysiwyg = "true";defparam \m_x|counter_neg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y14_N45cyclonev_lcell_comb \m_x|Selector5~1 (// Equation(s):// \m_x|Selector5~1_combout = ( \m_x|counter_neg [0] & ( (!\m_x|counter_neg [3] & (!\m_x|counter_neg [2] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [5]))) ) ).dataa(!\m_x|counter_neg [3]),.datab(!\m_x|counter_neg [2]),.datac(!\m_x|counter_neg [4]),.datad(!\m_x|counter_neg [5]),.datae(gnd),.dataf(!\m_x|counter_neg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector5~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector5~1 .extended_lut = "off";defparam \m_x|Selector5~1 .lut_mask = 64'h0000000080008000;defparam \m_x|Selector5~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N0cyclonev_lcell_comb \m_x|Selector5~0 (// Equation(s):// \m_x|Selector5~0_combout = ( !\m_x|counter_neg [5] & ( \m_x|counter_neg [2] & ( (!\m_x|counter_neg [3] & (!\m_x|counter_neg [4] & (\m_x|is_control~q & \m_x|counter_neg [0]))) ) ) ) # ( \m_x|counter_neg [5] & ( !\m_x|counter_neg [2] & (// (!\m_x|counter_neg [3] & (!\m_x|counter_neg [4] & \m_x|counter_neg [0])) ) ) ) # ( !\m_x|counter_neg [5] & ( !\m_x|counter_neg [2] & ( (!\m_x|counter_neg [3] & (!\m_x|counter_neg [4] & !\m_x|counter_neg [0])) ) ) ).dataa(!\m_x|counter_neg [3]),.datab(!\m_x|counter_neg [4]),.datac(!\m_x|is_control~q ),.datad(!\m_x|counter_neg [0]),.datae(!\m_x|counter_neg [5]),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector5~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector5~0 .extended_lut = "off";defparam \m_x|Selector5~0 .lut_mask = 64'h8800008800080000;defparam \m_x|Selector5~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N51cyclonev_lcell_comb \m_x|Selector5~2 (// Equation(s):// \m_x|Selector5~2_combout = ( \m_x|Selector5~0_combout & ( (!\m_x|counter_neg [1]) # (!\m_x|Selector5~1_combout ) ) ) # ( !\m_x|Selector5~0_combout & ( (\m_x|counter_neg [1] & !\m_x|Selector5~1_combout ) ) ).dataa(gnd),.datab(!\m_x|counter_neg [1]),.datac(!\m_x|Selector5~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\m_x|Selector5~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|Selector5~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|Selector5~2 .extended_lut = "off";defparam \m_x|Selector5~2 .lut_mask = 64'h30303030FCFCFCFC;defparam \m_x|Selector5~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N5dffeas \m_x|counter_neg[1] (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|Selector5~2_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|counter_neg [1]),.prn(vcc));// synopsys translate_offdefparam \m_x|counter_neg[1] .is_wysiwyg = "true";defparam \m_x|counter_neg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y14_N48cyclonev_lcell_comb \m_x|always2~0 (// Equation(s):// \m_x|always2~0_combout = LCELL(( \m_x|counter_neg [2] & ( (!\m_x|counter_neg [1] & (\m_x|Selector4~0_combout & \m_x|always3~0_combout )) ) )).dataa(!\m_x|counter_neg [1]),.datab(gnd),.datac(!\m_x|Selector4~0_combout ),.datad(!\m_x|always3~0_combout ),.datae(gnd),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|always2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|always2~0 .extended_lut = "off";defparam \m_x|always2~0 .lut_mask = 64'h00000000000A000A;defparam \m_x|always2~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N12cyclonev_lcell_comb \m_x|always1~0 (// Equation(s):// \m_x|always1~0_combout = LCELL(( \m_x|counter_neg [2] & ( (!\m_x|always3~0_combout & (!\m_x|counter_neg [1] & \m_x|Selector4~0_combout )) ) )).dataa(!\m_x|always3~0_combout ),.datab(!\m_x|counter_neg [1]),.datac(!\m_x|Selector4~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\m_x|counter_neg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|always1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|always1~0 .extended_lut = "off";defparam \m_x|always1~0 .lut_mask = 64'h0000000008080808;defparam \m_x|always1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N38dffeas \m_x|bit_c_0 (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_0~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_0 .is_wysiwyg = "true";defparam \m_x|bit_c_0 .power_up = "low";// synopsys translate_on// Location: FF_X23_Y14_N2dffeas \m_x|bit_c_2 (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|bit_c_0~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_2~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_2 .is_wysiwyg = "true";defparam \m_x|bit_c_2 .power_up = "low";// synopsys translate_on// Location: FF_X23_Y14_N8dffeas \m_x|control_r[2] (.clk(\m_x|always1~0_combout ),.d(gnd),.asdata(\m_x|bit_c_2~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|is_control~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_r[2] .is_wysiwyg = "true";defparam \m_x|control_r[2] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y15_N34dffeas \m_x|control_p_r[2] (.clk(\m_x|always2~0_combout ),.d(gnd),.asdata(\m_x|control_r [2]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|is_control~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_p_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_p_r[2] .is_wysiwyg = "true";defparam \m_x|control_p_r[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y15_N12cyclonev_lcell_comb \m_x|ready_control_p_r~0 (// Equation(s):// \m_x|ready_control_p_r~0_combout = ( \m_x|always2~0_combout & ( (\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ) ) ) # ( !\m_x|always2~0_combout & ( (\m_x|always1~0_combout & ((\m_x|ready_control_p_r~q ) # (\m_x|is_control~q ))) ) ).dataa(!\m_x|is_control~q ),.datab(!\m_x|always1~0_combout ),.datac(!\m_x|ready_control_p_r~q ),.datad(gnd),.datae(gnd),.dataf(!\m_x|always2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_control_p_r~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_control_p_r~0 .extended_lut = "off";defparam \m_x|ready_control_p_r~0 .lut_mask = 64'h131313135F5F5F5F;defparam \m_x|ready_control_p_r~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y15_N20dffeas \m_x|ready_control_p_r (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|ready_control_p_r~0_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|ready_control_p_r~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|ready_control_p_r .is_wysiwyg = "true";defparam \m_x|ready_control_p_r .power_up = "low";// synopsys translate_on// Location: FF_X21_Y15_N32dffeas \m_x|control[2] (.clk(\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|control_p_r [2]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|ready_control_p_r~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control[2] .is_wysiwyg = "true";defparam \m_x|control[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y15_N0cyclonev_lcell_comb \m_x|control_l_r[2]~feeder (// Equation(s):// \m_x|control_l_r[2]~feeder_combout = ( \m_x|control [2] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_l_r[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_l_r[2]~feeder .extended_lut = "off";defparam \m_x|control_l_r[2]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control_l_r[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y15_N2dffeas \m_x|control_l_r[2] (.clk(\m_x|always3~0_combout ),.d(\m_x|control_l_r[2]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|ready_control_p_r~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_l_r [2]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_l_r[2] .is_wysiwyg = "true";defparam \m_x|control_l_r[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N6cyclonev_lcell_comb \m_x|info[12]~feeder (// Equation(s):// \m_x|info[12]~feeder_combout = ( \m_x|control_l_r [2] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control_l_r [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|info[12]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|info[12]~feeder .extended_lut = "off";defparam \m_x|info[12]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|info[12]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N15cyclonev_lcell_comb \m_x|ready_data_p_r~0 (// Equation(s):// \m_x|ready_data_p_r~0_combout = ( \m_x|Equal1~0_combout & ( (!\m_x|always3~0_combout & (!\m_x|counter_neg [1] & (\m_x|counter_neg [5] & !\m_x|counter_neg [2]))) ) ).dataa(!\m_x|always3~0_combout ),.datab(!\m_x|counter_neg [1]),.datac(!\m_x|counter_neg [5]),.datad(!\m_x|counter_neg [2]),.datae(gnd),.dataf(!\m_x|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data_p_r~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data_p_r~0 .extended_lut = "off";defparam \m_x|ready_data_p_r~0 .lut_mask = 64'h0000000008000800;defparam \m_x|ready_data_p_r~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N39cyclonev_lcell_comb \m_x|ready_data_p (// Equation(s):// \m_x|ready_data_p~combout = LCELL(( \m_x|counter_neg [5] & ( \m_x|always3~0_combout & ( (!\m_x|always2~0_combout & (\m_x|Equal1~0_combout & (!\m_x|counter_neg [2] & !\m_x|counter_neg [1]))) ) ) )).dataa(!\m_x|always2~0_combout ),.datab(!\m_x|Equal1~0_combout ),.datac(!\m_x|counter_neg [2]),.datad(!\m_x|counter_neg [1]),.datae(!\m_x|counter_neg [5]),.dataf(!\m_x|always3~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data_p~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data_p .extended_lut = "off";defparam \m_x|ready_data_p .lut_mask = 64'h0000000000002000;defparam \m_x|ready_data_p .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y14_N33cyclonev_lcell_comb \m_x|ready_data_p_r~1 (// Equation(s):// \m_x|ready_data_p_r~1_combout = ( \m_x|ready_data_p~combout & ( (!\m_x|is_control~q ) # (\m_x|ready_data_p_r~q ) ) ) # ( !\m_x|ready_data_p~combout & ( (\m_x|ready_data_p_r~0_combout & (!\m_x|always1~0_combout & ((!\m_x|is_control~q ) #// (\m_x|ready_data_p_r~q )))) ) ).dataa(!\m_x|ready_data_p_r~0_combout ),.datab(!\m_x|always1~0_combout ),.datac(!\m_x|ready_data_p_r~q ),.datad(!\m_x|is_control~q ),.datae(gnd),.dataf(!\m_x|ready_data_p~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|ready_data_p_r~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|ready_data_p_r~1 .extended_lut = "off";defparam \m_x|ready_data_p_r~1 .lut_mask = 64'h44044404FF0FFF0F;defparam \m_x|ready_data_p_r~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y14_N41dffeas \m_x|ready_data_p_r (.clk(!\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|ready_data_p_r~1_combout ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|ready_data_p_r~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|ready_data_p_r .is_wysiwyg = "true";defparam \m_x|ready_data_p_r .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y15_N9cyclonev_lcell_comb \m_x|data_l_r[7]~0 (// Equation(s):// \m_x|data_l_r[7]~0_combout = ( !\m_x|ready_data_p_r~q & ( !\m_x|ready_control_p_r~q ) ).dataa(gnd),.datab(gnd),.datac(!\m_x|ready_control_p_r~q ),.datad(gnd),.datae(gnd),.dataf(!\m_x|ready_data_p_r~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|data_l_r[7]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|data_l_r[7]~0 .extended_lut = "off";defparam \m_x|data_l_r[7]~0 .lut_mask = 64'hF0F0F0F000000000;defparam \m_x|data_l_r[7]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N8dffeas \m_x|info[12] (.clk(\m_x|always3~0_combout ),.d(\m_x|info[12]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|data_l_r[7]~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|info [12]),.prn(vcc));// synopsys translate_offdefparam \m_x|info[12] .is_wysiwyg = "true";defparam \m_x|info[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N33cyclonev_lcell_comb \u0|data_info|read_mux_out[12] (// Equation(s):// \u0|data_info|read_mux_out [12] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [12]) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),.datab(gnd),.datac(!\m_x|info [12]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|data_info|read_mux_out [12]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|data_info|read_mux_out[12] .extended_lut = "off";defparam \u0|data_info|read_mux_out[12] .lut_mask = 64'h0A0A0A0A00000000;defparam \u0|data_info|read_mux_out[12] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N35dffeas \u0|data_info|readdata[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|data_info|read_mux_out [12]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|data_info|readdata [12]),.prn(vcc));// synopsys translate_offdefparam \u0|data_info|readdata[12] .is_wysiwyg = "true";defparam \u0|data_info|readdata[12] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y16_N34dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|data_info|readdata [12]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [12]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[12] .power_up = "low";// synopsys translate_on// Location: FF_X22_Y16_N38dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~12_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q &// !\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1].dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y36_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y36_N44dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y36_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|cp_ready~0_combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_info_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFF55FFFF0000;defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y36_N38dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y38_N14dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y16_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout = ( !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_info_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .lut_mask = 64'h00FF00FF00000000;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y16_N41dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y14_N36cyclonev_lcell_comb \m_x|bit_c_1~feeder (// Equation(s):// \m_x|bit_c_1~feeder_combout = ( \A_SPW_TOP|SPW|TX|tx_dout_e~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\A_SPW_TOP|SPW|TX|tx_dout_e~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|bit_c_1~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|bit_c_1~feeder .extended_lut = "off";defparam \m_x|bit_c_1~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|bit_c_1~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y14_N38dffeas \m_x|bit_c_1 (.clk(\m_x|always3~0_combout ),.d(\m_x|bit_c_1~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_1~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_1 .is_wysiwyg = "true";defparam \m_x|bit_c_1 .power_up = "low";// synopsys translate_on// Location: FF_X25_Y14_N31dffeas \m_x|bit_c_3 (.clk(\m_x|always3~0_combout ),.d(gnd),.asdata(\m_x|bit_c_1~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\m_x|bit_c_3~q ),.prn(vcc));// synopsys translate_offdefparam \m_x|bit_c_3 .is_wysiwyg = "true";defparam \m_x|bit_c_3 .power_up = "low";// synopsys translate_on// Location: FF_X23_Y14_N20dffeas \m_x|control_r[3] (.clk(\m_x|always1~0_combout ),.d(gnd),.asdata(\m_x|bit_c_3~q ),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|is_control~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_r[3] .is_wysiwyg = "true";defparam \m_x|control_r[3] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y15_N16dffeas \m_x|control_p_r[3] (.clk(\m_x|always2~0_combout ),.d(gnd),.asdata(\m_x|control_r [3]),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\m_x|is_control~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_p_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_p_r[3] .is_wysiwyg = "true";defparam \m_x|control_p_r[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y15_N15cyclonev_lcell_comb \m_x|control[3]~feeder (// Equation(s):// \m_x|control[3]~feeder_combout = ( \m_x|control_p_r [3] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control_p_r [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control[3]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control[3]~feeder .extended_lut = "off";defparam \m_x|control[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control[3]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y15_N17dffeas \m_x|control[3] (.clk(\m_x|always3~0_combout ),.d(\m_x|control[3]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|ready_control_p_r~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control[3] .is_wysiwyg = "true";defparam \m_x|control[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y15_N3cyclonev_lcell_comb \m_x|control_l_r[3]~feeder (// Equation(s):// \m_x|control_l_r[3]~feeder_combout = ( \m_x|control [3] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|control_l_r[3]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|control_l_r[3]~feeder .extended_lut = "off";defparam \m_x|control_l_r[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|control_l_r[3]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y15_N4dffeas \m_x|control_l_r[3] (.clk(\m_x|always3~0_combout ),.d(\m_x|control_l_r[3]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|ready_control_p_r~q ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|control_l_r [3]),.prn(vcc));// synopsys translate_offdefparam \m_x|control_l_r[3] .is_wysiwyg = "true";defparam \m_x|control_l_r[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N9cyclonev_lcell_comb \m_x|info[13]~feeder (// Equation(s):// \m_x|info[13]~feeder_combout = ( \m_x|control_l_r [3] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\m_x|control_l_r [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\m_x|info[13]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \m_x|info[13]~feeder .extended_lut = "off";defparam \m_x|info[13]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \m_x|info[13]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N11dffeas \m_x|info[13] (.clk(\m_x|always3~0_combout ),.d(\m_x|info[13]~feeder_combout ),.asdata(vcc),.clrn(!\db_system_spwulight_b|aux_pb~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\m_x|data_l_r[7]~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\m_x|info [13]),.prn(vcc));// synopsys translate_offdefparam \m_x|info[13] .is_wysiwyg = "true";defparam \m_x|info[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y16_N3cyclonev_lcell_comb \u0|data_info|read_mux_out[13] (// Equation(s):// \u0|data_info|read_mux_out [13] = ( !\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2] & (// (!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3] & \m_x|info [13]) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [3]),.datab(gnd),.datac(!\m_x|info [13]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|data_info|read_mux_out [13]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|data_info|read_mux_out[13] .extended_lut = "off";defparam \u0|data_info|read_mux_out[13] .lut_mask = 64'h0A0A0A0A00000000;defparam \u0|data_info|read_mux_out[13] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y16_N5dffeas \u0|data_info|readdata[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|data_info|read_mux_out [13]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|data_info|readdata [13]),.prn(vcc));// synopsys translate_offdefparam \u0|data_info|readdata[13] .is_wysiwyg = "true";defparam \u0|data_info|readdata[13] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y16_N4dffeas \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|data_info|readdata [13]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y16_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] & ( (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1] &// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[1][13]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y16_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0] ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|read~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0F0F0F0F;defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y16_N35dffeas \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem~13_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y16_N33cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout = ( \u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] & ( (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &// ((\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ) # (\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13] & (// (\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout & \u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q )) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|always4~0_combout ),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rdata_fifo|mem[0][13]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_translator|av_readdata_pre [13]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .lut_mask = 64'h0050005005550555;defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~33 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y26_N29dffeas \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[1][106] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y25_N44dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~12_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][107] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal13~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal13~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal13~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal13~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal13~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|router_001|Equal13~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~3 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~3_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~3 .lut_mask = 64'h0000000000550055;defparam \u0|mm_interconnect_0|router_001|Equal1~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_channel[16]~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]// & (\u0|mm_interconnect_0|router_001|Equal2~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR// [18] & (\u0|mm_interconnect_0|router_001|Equal2~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .lut_mask = 64'h00000A0000000800;defparam \u0|mm_interconnect_0|router_001|src_channel[16]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y31_N41dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[16] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16] & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & (// \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.dataf(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .lut_mask = 64'h0000000033331111;defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_016|saved_grant[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N23dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N11dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q &// \u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|waitrequest_reset_override~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .lut_mask = 64'h1111111100000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N56dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel// [16] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [16]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .lut_mask = 64'h0F000F000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout & (// \u0|mm_interconnect_0|router_001|src_channel[16]~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~1_combout ),.dataf(!\u0|mm_interconnect_0|router_001|src_channel[16]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000000101;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N59dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y38_N26dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h02020A0A02020A0A;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00000000F5F5F5F5;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N5dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .lut_mask = 64'hF0F0F0F050505050;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1])) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFAAFFAAAFAAAFAA;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y37_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y37_N53dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h31DF31DF20CE20CE;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N11dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N50dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .lut_mask = 64'h4505BFFF4000BAFA;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h1BF51BF50AE40AE4;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N35dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N13dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h11B1FF5F00A0EE4E;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~4_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8800000000000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h3370337033003300;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N47dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00AA00AA10FA10FA;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N20dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CF33CF30CC30CC;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N8dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N29dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][74]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h02025757A2A2F7F7;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used// [0] ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFAFAFAFA;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N47dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N59dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N41dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h0D08080D07020207;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N32dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N23dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N20dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N44dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N8dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y38_N56dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N11dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ))).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3F3F3F3FC0C0C0C0;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q $// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q $// (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ))))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h008700FF00870000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N8dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h77887788FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00000000F5A0F5A0;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N59dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1040154515451040;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N20dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000220000007250;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N2dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00AF00AF00FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5500555500000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y38_N17dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y38_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y38_N5dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y38_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y38_N44dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ) #// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|comb~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFFFE0E0;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y38_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )))) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout )))) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout $ (((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout & !\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout// ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h009C009C23BF23BF;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N38dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1].dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N29dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X19_Y38_N26dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )// # ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ))) ) )// ) # ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ( (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout & \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) ) #// ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_016|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFF00011FFF1;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y38_N32dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y38_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000AA80AA80;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y38_N56dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y38_N34dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y38_N29dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal12~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal12~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|mm_interconnect_0|router_001|Equal2~0_combout &// (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|router_001|Equal1~1_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|mm_interconnect_0|router_001|Equal2~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal12~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal12~0 .lut_mask = 64'h0000000100000000;defparam \u0|mm_interconnect_0|router_001|Equal12~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y31_N50dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[21] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y29_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal12~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [21]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal12~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .lut_mask = 64'h0000000055055505;defparam \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y24_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y24_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y24_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h000000000C0C0C0C;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y24_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout// ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y24_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y24_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout// & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000000F0F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y24_N23dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y24_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y24_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFF0CFF0CFFCCFFCC;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y24_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y24_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal7~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16])) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal7~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal7~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal7~1 .lut_mask = 64'h00000000C000C000;defparam \u0|mm_interconnect_0|router_001|Equal7~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal7~2 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal7~2_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal7~1_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &// \u0|mm_interconnect_0|router_001|Equal1~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal7~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal7~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal7~2 .lut_mask = 64'h0000000000050005;defparam \u0|mm_interconnect_0|router_001|Equal7~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y31_N53dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal7~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4] &// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [4]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .lut_mask = 64'h00FF00FF000F000F;defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &// (\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal7~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datac(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src4_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|cmd_demux_001|src4_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y28_N21cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~7 (// Equation(s):// \u0|mm_interconnect_0|router|Equal7~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]// & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q &// (((!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_AWADDR [16])))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst// [17])) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [17]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [17]),.datad(!\u0|hps_0|fpga_interfaces|h2f_AWADDR [16]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|address_burst [16]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal7~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal7~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal7~7 .lut_mask = 64'hE222E222C000C000;defparam \u0|mm_interconnect_0|router|Equal7~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y24_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_015|arb|top_priority_reg[0]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y21_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y21_N53dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y24_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( \u0|mm_interconnect_0|router_001|Equal21~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]))) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [15]),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.dataf(!\u0|mm_interconnect_0|router_001|Equal21~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .lut_mask = 64'h0000000000000B0B;defparam \u0|mm_interconnect_0|cmd_mux_015|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y24_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y24_N5dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N9cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal17~0 (// Equation(s):// \u0|mm_interconnect_0|router|Equal17~0_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & (\u0|mm_interconnect_0|router|Equal14~0_combout &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal17~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal17~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal17~0 .lut_mask = 64'h0000000000050005;defparam \u0|mm_interconnect_0|router|Equal17~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y27_N11dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router|Equal17~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[11] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src11_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_WVALID [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [11]),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .lut_mask = 64'h000000000F030F03;defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y27_N18cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src11_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout = ( \u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout & \u0|mm_interconnect_0|router|Equal14~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),.datad(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux|src11_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src11_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|cmd_demux|src11_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y27_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout = !\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout.dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_011|arb|grant[1]~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .lut_mask = 64'hFF00FF00FF00FF00;defparam \u0|mm_interconnect_0|cmd_mux_011|arb|top_priority_reg[0]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal17~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [17] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal17~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal17~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal17~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|router_001|Equal17~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal17~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal17~1_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]// & (\u0|mm_interconnect_0|router_001|Equal17~0_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datac(!\u0|mm_interconnect_0|router_001|Equal17~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datae(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal17~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal17~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal17~1 .lut_mask = 64'h0000000000000002;defparam \u0|mm_interconnect_0|router_001|Equal17~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N20dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal17~1_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[11] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y27_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & \u0|mm_interconnect_0|router_001|Equal17~1_combout ) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|mm_interconnect_0|router_001|Equal17~1_combout// )) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datac(!\u0|mm_interconnect_0|router_001|Equal17~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src11_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .lut_mask = 64'h0404040405050505;defparam \u0|mm_interconnect_0|cmd_demux_001|src11_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARLEN [3] & (\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|hps_0|fpga_interfaces|h2f_ARLEN [2])) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [3]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .lut_mask = 64'h0000000000110011;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y27_N39cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .lut_mask = 64'h55555555AAAAAAAA;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y27_N41dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add7~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y27_N12cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q// ) # (\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] &// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_AWLEN [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3] & ( (\u0|hps_0|fpga_interfaces|h2f_AWLEN [1] &// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ) ) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|sop_enable~q ),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_AWLEN [0]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|burst_bytecount [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .lut_mask = 64'h3030C0C03F3FCFCF;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal19~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal19~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (\u0|mm_interconnect_0|router_001|Equal7~0_combout & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datae(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal19~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal19~0 .lut_mask = 64'h0000000000000001;defparam \u0|mm_interconnect_0|router_001|Equal19~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N49dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal19~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[13] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal19~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [13]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|router_001|Equal19~0_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .lut_mask = 64'h0000515100005151;defparam \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y34_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000001010101;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N10dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y34_N2dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0000000030F030F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N35dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000011111111;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N17dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N29dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000F000F00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00F000F000FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used// [1])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h03CF03CF01670167;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N26dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y34_N14dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFF000F000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N35dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X19_Y34_N11dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y34_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [3] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [0])) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1].dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N5dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFFCF00CF00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N11dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 (// Equation(s):// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [1] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .lut_mask = 64'h0000FFFFFFFF0000;defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h1DD11DD10CC00CC0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N17dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) )// # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout// )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout// )))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h3305CC050005FF05;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hB4B4B4B4F0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout// ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|saved_grant// [1] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hCC00CC00CC55CC55;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y34_N59dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N20dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout &// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout// $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0CC00CC01DD11DD1;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N13dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) )// # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout// )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))// ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout// )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))// ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h0F11F0110011FF11;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00FF00FF80FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y35_N44dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~2_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h5555044451110000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N2dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F020F0F0FDF0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hAA00AA00AAAAAAAA;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFEE22EE22;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N11dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFE22EE22E;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N17dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h0000FFFFC0AA3FAA;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0202FEFEF2F20E0E;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N25dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h0C00F3FF0CAAF3AA;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h554C554C55005500;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N5dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF040C040C;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N32dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001FF01;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00E000E000A000A0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N38dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1])) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h01FF01FF01010101;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N53dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0C00AAAA3FFFAFAF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout &// ( \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .lut_mask = 64'h00FF00FF0AFA0AFA;defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y34_N35dffeas \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_013|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q )// # ((\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &// ( (!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_013|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_013|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .lut_mask = 64'hF0C0F0C0F0F3F0F3;defparam \u0|mm_interconnect_0|cmd_mux_013|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y31_N41dffeas \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_013|saved_grant[1]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_013|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_013|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y34_N20dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [1] ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [3]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [2]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [3]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'h77FF7FFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N38dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ) #// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h000F000FCCCFCCCF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0F000F00;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|wait_latency_counter [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000030303030;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] &// ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h1110111033303330;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00CC00CC0CCC0CCC;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N14dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]// $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg// [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h03F303F3C3FFC3FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y35_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N53dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y35_N35dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y35_N44dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N14dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y35_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h000A555FA0AAF5FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N17dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N23dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X21_Y35_N2dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000F3A2F3A2;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N41dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0E040B01040E010B;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N32dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CF0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout// ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) )// ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0C030A0A03030A0A;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N8dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h6A6A6A6AAAAAAAAA;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ) #// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h5550555000500050;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N2dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000440000007430;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N20dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3 .lut_mask = 64'hA0A0000000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3_combout ) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5505550555555555;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h1020132313231020;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y36_N56dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000000008000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N23dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N29dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y36_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &// ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h0080000000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout & (// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|comb~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h00FA00FA00AA00AA;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y34_N20dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0] &// ((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .lut_mask = 64'hFA00FA0000000000;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N2dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y22_N53dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h33CC33CC30FC30FC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N38dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N51cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h404F404F707F707F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N12cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .lut_mask = 64'h0555055555555555;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|rsp_demux_010|WideOr0~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout )// ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFF0FFF0FFF00FF00;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N41dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N21cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h0EF20EF202FE02FE;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N23dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h00B8FF740030FFFC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0080008000800080;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h02FE02FECE32CE32;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N20dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y22_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout = (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q )))).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0257025702570257;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N29dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y22_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N23dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y22_N50dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N20dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8800880000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N47dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N12cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])// # ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0022FFEEF0220FEE;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y22_N13dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N32dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3120203113020213;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N44dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CCCCCCCCC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N6cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) )// # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00A500CC005500CC;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N8dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N39cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) )// ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) )// ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0208070D070D0208;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N56dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000220000007250;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N50dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y20_N53dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N36cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000FF3FFF3F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N12cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C0F0C0F00000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N14dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N27cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FA05FA0FF00FF00;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N3cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ) #// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add0~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y20_N5dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q & ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y22_N32dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// )))) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|cp_ready~0_combout ),.datag(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0C00F0F00C00F5F5;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & (// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout// ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout & (// (\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout & (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~0_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_010|src_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00130013005F005F;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y22_N23dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_010|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y22_N20dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout &// ( (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout & (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout &// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q )) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~0_combout ),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|comb~0_combout ),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00F000FF00C0;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) # (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ) ) # ( \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout & ( ((!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|uncompressor|always0~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000DDFFFFFFFFFF;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y20_N26dffeas \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y20_N39cyclonev_lcell_comb \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0] & ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_translator|read_latency_shift_reg [0]),.dataf(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .lut_mask = 64'hFFAA000000000000;defparam \u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y24_N33cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_demux_010|src1_valid (// Equation(s):// \u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout = ( !\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|write_data_fifo_tx_s1_agent|rp_valid~combout ),.dataf(!\u0|mm_interconnect_0|rsp_demux_010|src0_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_demux_010|src1_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .lut_mask = 64'hFFFF000000000000;defparam \u0|mm_interconnect_0|rsp_demux_010|src1_valid .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y24_N56dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: HPSINTERFACEHPS2FPGA_X32_Y24_N111cyclonev_hps_interface_hps2fpga \u0|hps_0|fpga_interfaces|hps2fpga (.arready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|cmd_sink_ready~0_combout ),.awready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~0_combout ),.bvalid(\u0|mm_interconnect_0|rsp_mux|WideOr1~combout ),.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.rlast(\u0|mm_interconnect_0|rsp_mux_001|src_payload [0]),.rvalid(\u0|mm_interconnect_0|rsp_mux_001|WideOr1~combout ),.wready(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1_combout ),.bid({\u0|mm_interconnect_0|rsp_mux|src_data [116],\u0|mm_interconnect_0|rsp_mux|src_data [115],\u0|mm_interconnect_0|rsp_mux|src_data [114],\u0|mm_interconnect_0|rsp_mux|src_data [113],\u0|mm_interconnect_0|rsp_mux|src_data [112],\u0|mm_interconnect_0|rsp_mux|src_data [111],\u0|mm_interconnect_0|rsp_mux|src_data [110],\u0|mm_interconnect_0|rsp_mux|src_data [109],\u0|mm_interconnect_0|rsp_mux|src_data [108],\u0|mm_interconnect_0|rsp_mux|src_data [107],\u0|mm_interconnect_0|rsp_mux|src_data [106],\u0|mm_interconnect_0|rsp_mux|src_data [105]}),.bresp({gnd,gnd}),.port_size_config({gnd,gnd}),.rdata({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,\u0|mm_interconnect_0|rsp_mux_001|src_payload~33_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~32_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~31_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~30_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_payload~29_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[8]~96_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[7]~217_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[6]~221_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[5]~84_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[4]~225_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[3]~229_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[2]~233_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[1]~237_combout ,\u0|mm_interconnect_0|rsp_mux_001|src_data[0]~30_combout }),.rid({\u0|mm_interconnect_0|rsp_mux_001|src_data [116],\u0|mm_interconnect_0|rsp_mux_001|src_data [115],\u0|mm_interconnect_0|rsp_mux_001|src_data [114],\u0|mm_interconnect_0|rsp_mux_001|src_data [113],\u0|mm_interconnect_0|rsp_mux_001|src_data [112],\u0|mm_interconnect_0|rsp_mux_001|src_data [111],\u0|mm_interconnect_0|rsp_mux_001|src_data [110],\u0|mm_interconnect_0|rsp_mux_001|src_data [109],\u0|mm_interconnect_0|rsp_mux_001|src_data [108],\u0|mm_interconnect_0|rsp_mux_001|src_data [107],\u0|mm_interconnect_0|rsp_mux_001|src_data [106],\u0|mm_interconnect_0|rsp_mux_001|src_data [105]}),.rresp({gnd,gnd}),.arvalid(\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.awvalid(\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),.bready(\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.rready(\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.wlast(\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.wvalid(\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),.araddr(\u0|hps_0|fpga_interfaces|hps2fpga_ARADDR_bus ),.arburst(\u0|hps_0|fpga_interfaces|hps2fpga_ARBURST_bus ),.arcache(),.arid(\u0|hps_0|fpga_interfaces|hps2fpga_ARID_bus ),.arlen(\u0|hps_0|fpga_interfaces|hps2fpga_ARLEN_bus ),.arlock(),.arprot(),.arsize(\u0|hps_0|fpga_interfaces|hps2fpga_ARSIZE_bus ),.awaddr(\u0|hps_0|fpga_interfaces|hps2fpga_AWADDR_bus ),.awburst(\u0|hps_0|fpga_interfaces|hps2fpga_AWBURST_bus ),.awcache(),.awid(\u0|hps_0|fpga_interfaces|hps2fpga_AWID_bus ),.awlen(\u0|hps_0|fpga_interfaces|hps2fpga_AWLEN_bus ),.awlock(),.awprot(),.awsize(\u0|hps_0|fpga_interfaces|hps2fpga_AWSIZE_bus ),.wdata(\u0|hps_0|fpga_interfaces|hps2fpga_WDATA_bus ),.wid(),.wstrb(\u0|hps_0|fpga_interfaces|hps2fpga_WSTRB_bus ));// synopsys translate_offdefparam \u0|hps_0|fpga_interfaces|hps2fpga .data_width = 32;// synopsys translate_on// Location: MLABCELL_X14_Y24_N3cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) #// ( !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( !\u0|hps_0|fpga_interfaces|h2f_ARID [11] & (// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .lut_mask = 64'h000055550F0F5F5F;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & (// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h0033003355775577;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF00FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N8dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N56dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (// (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h30FF30FF30303030;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h0AA00AA05FF55FF5;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N2dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y22_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h0033003355775577;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] $// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout )))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h03F303F3A353A353;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N32dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [4] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hFF5FFF5F00A000A0;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1])) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hF1F10101F1FF010F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N50dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .lut_mask = 64'h0303F3F3F3F30303;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hF000F000F0F0F0F0;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N53dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|local_write~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .lut_mask = 64'h000A000A0A000A00;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y22_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [35] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y22_N17dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y22_N56dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .lut_mask = 64'h0F0F0F0F5F5F5F5F;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y22_N35dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y24_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .lut_mask = 64'h0033003355775577;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y24_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_data [88] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) ) #// ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( !\u0|hps_0|fpga_interfaces|h2f_AWSIZE// [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .lut_mask = 64'h00000F0F55555F5F;defparam \u0|mm_interconnect_0|cmd_mux_015|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y24_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [87] & ( !\u0|mm_interconnect_0|cmd_mux_015|src_data [88] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_015|src_data [87]),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_data [88]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFF000000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y22_N8dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .lut_mask = 64'h7575757500000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N2dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000FF04FF04;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000000100010;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N14dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h33CF33CF30CC30CC;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N8dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h30CF30CF22EE22EE;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N41dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] $// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h3333C3AA333333AA;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N38dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00C000C000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h02FE02FEF20EF20E;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y22_N19dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y22_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])// # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0022FFEEC0E23F2E;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8800000000000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0])))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0013FFFF0013CCFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N32dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00000000FAAAFAAA;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0F3F0F3F00000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) )// # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout// & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout )// ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h775577557F5F7F5F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N8dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_015|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (// \u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] ) ) # ( \u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WLAST [0] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .lut_mask = 64'h00000F0FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_015|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N49dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_015|src_payload [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )// # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000AA80AA80;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &// ( (!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h000000003B0A3B0A;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout// & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~3_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFF35FF3500000000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (// ((\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h0303030357575757;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N59dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h11BB11BBB11BB11B;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y22_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout &// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~4_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0F0F8F0F0F0F0F0F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y22_N26dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q// )))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ) #// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q// )))) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h01F101F10BFB0BFB;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y22_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h02EE02EE00CC00CC;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y22_N59dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y22_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout & ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|cp_ready~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h3F3F0000003F0000;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y24_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (// \u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ))) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout & (// !\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0] & (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ((\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_015|saved_grant [0]),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(!\u0|mm_interconnect_0|cmd_demux|src15_valid~1_combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_015|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h00000105030F030F;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y24_N4dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_015|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y24_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00330033CCFFCCFF;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y22_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used// [0] ) ).dataa(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFAAFFAA;defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y24_N35dffeas \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y24_N30cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213_combout = ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ) ) # (// !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & ( \u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout &// \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( \u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & (// (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ) # ( !\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q & (// !\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout & ( (\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout & \u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_015|src1_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_tx_enable_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|clock_sel_s1_agent_rsp_fifo|mem[0][116]~q ),.dataf(!\u0|mm_interconnect_0|rsp_demux_018|src1_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213 .lut_mask = 64'h050505050505FFFF;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~213 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y32_N50dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y32_N38dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y28_N9cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal13~1 (// Equation(s):// \u0|mm_interconnect_0|router|Equal13~1_combout = ( \u0|mm_interconnect_0|router|Equal13~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|router|Equal7~6_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|router|Equal13~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal13~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal13~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal13~1 .lut_mask = 64'h0000000000000505;defparam \u0|mm_interconnect_0|router|Equal13~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y28_N11dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router|Equal13~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y28_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src7_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_AWVALID [0] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7] & ( \u0|hps_0|fpga_interfaces|h2f_WVALID [0] ) ) ) # (// \u0|hps_0|fpga_interfaces|h2f_AWVALID [0] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_WVALID [0]) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WVALID [0]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_AWVALID [0]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .lut_mask = 64'h00000A0A00000F0F;defparam \u0|mm_interconnect_0|cmd_demux|src7_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant// [0] & (\u0|mm_interconnect_0|router|Equal13~0_combout & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout & \u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datab(!\u0|mm_interconnect_0|router|Equal13~0_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_demux|src7_valid~0_combout ),.datae(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .lut_mask = 64'h0000000000000001;defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal13~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7])))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [7]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal13~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .lut_mask = 64'h0000000011011101;defparam \u0|mm_interconnect_0|cmd_mux_007|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h000F000F00FF00FF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y33_N23dffeas \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h000000000FF00FF0;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y33_N8dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N44dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|local_write (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|link_start_s1_agent|local_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .lut_mask = 64'h0F000F0000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q &// ((\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout & (// (\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout & (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]) #// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1])))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_translator|read_latency_shift_reg~0_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|m0_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h00510051003F003F;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y33_N35dffeas \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (// ((\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) #// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (// ((\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]))) #// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .lut_mask = 64'h3733000073330000;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF0F0F0F0F;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y29_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) #// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hCFCFCFCF00000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y29_N50dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N11dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .lut_mask = 64'h33F333F300F000F0;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout = (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))))// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout// )))).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~7_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .lut_mask = 64'h278D278D278D278D;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N53dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y32_N50dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h000F000F333F333F;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h208A208A75DF75DF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hCF30CF30FF00FF00;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datae(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hF0F5F3F700050307;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N38dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0A000A0000000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N8dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h30C030C03FCF3FCF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h000F000F555F555F;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N29dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) )// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) )// ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h3055CF553055CF55;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout &// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~8_combout ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h00008000FFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y32_N56dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WLAST// [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .lut_mask = 64'h03030303FFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_007|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N8dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_payload [0]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout// & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00FF00FF53535353;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])))) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ((\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0111FFFF0111DDDD;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N56dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h00000000000C000C;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FC00FC00F000F0;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// )) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h555F555F00000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1])))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5500550055105510;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & ( ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h505050FFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N53dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) )// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h55555555AFA0AFA0;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N26dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) )// # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))// ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .lut_mask = 64'h0000FFFFFA0A0AFA;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N29dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y34_N2dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))// # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFA0CC5FCC;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N41dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0A000A0000000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .lut_mask = 64'h0202FEFEF2F20E0E;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N19dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )))) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0C2EF3E20022FFEE;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout &// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~1_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )// # ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) # (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) )// ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )// ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h0022EEEE0000CCCC;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N5dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C080C0808080808;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (((!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h020F020F02020202;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .lut_mask = 64'h5555555577777777;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N44dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) # ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB// [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .lut_mask = 64'h000F000FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N41dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [33]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .lut_mask = 64'h5555555577777777;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N11dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y29_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]) ) ) ) #// ( !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( !\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0] & (// \u0|mm_interconnect_0|cmd_mux_007|saved_grant [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .lut_mask = 64'h000033330F0F3F3F;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_007|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_007|src_data [88] = (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & (((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])))) # (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// (((\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & \u0|mm_interconnect_0|cmd_mux_007|saved_grant [0])) # (\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]))).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datab(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_007|saved_grant [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .lut_mask = 64'h111F111F111F111F;defparam \u0|mm_interconnect_0|cmd_mux_007|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_007|src_data [87] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_007|src_data [87]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_data [88]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y31_N20dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] &// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .lut_mask = 64'h0050005000A000A0;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y31_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~1_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .lut_mask = 64'h0C000C00CCCCCCCC;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout &// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout &// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F050305030;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) #// ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N17dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h5F5F5F5F55555555;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N35dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h23002300AF00AF00;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0F00F1F10000F1F1;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout &// ((\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ) # (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~1_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_007|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0105010511551155;defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y29_N10dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_007|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used// [1]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~21_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N17dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][74]~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h4444777700CC33FF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N17dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X25_Y34_N32dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N32dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3202310102320131;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N56dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [3] ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h0F0FF0F0FFFF0000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N56dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) #// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N29dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ) #// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// )) ) ) ) # ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) #// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h5404045404045454;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N50dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout = !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [4] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h6AAA6AAA6AAA6AAA;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N8dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][77]~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h0000333300CC33FF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y34_N35dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~8_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h66CC66CCCCCCCCCC;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout// )) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) # (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00FC00FC00300030;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N20dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y34_N47dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q & ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[1][78]~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000033330C0C3F3F;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N14dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [4] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) #// ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N44dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N38dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout// & ( (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )))) #// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout &// (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000500000005C0C;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N1dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h0C0F0C0F0F0F0F0F;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )))// ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00F300F300000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y34_N23dffeas \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout = (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q// ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q & (// (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q & (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q &// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][77]~q ),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h2000000000000000;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout// & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & !\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout & (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q & !\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout & ( (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q &// ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout & (// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout & ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][66]~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|comb~0_combout ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0F0F0F0C0F000F00;defparam \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y33_N41dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y33_N46dffeas \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_007|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datad(gnd),.datae(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .lut_mask = 64'h0505555505055555;defparam \u0|mm_interconnect_0|link_start_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N24cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & (// (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] &// (\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] $ (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] &// (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout & ( (\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1] &// \u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q )) ) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [0]),.datab(!\u0|mm_interconnect_0|link_start_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .lut_mask = 64'h0404040408040404;defparam \u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|local_write~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout & (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ) #// (\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|cp_ready~4_combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|nonposted_write_endofpacket~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h150015003F003F00;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout & (// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ) #// (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1])))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00BF00BFFFFFFFFF;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y34_N44dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|always0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|link_start_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y32_N56dffeas \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y33_N47dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_013|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_013|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .lut_mask = 64'h0000555500005555;defparam \u0|mm_interconnect_0|cmd_mux_013|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y33_N16dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_013|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y33_N50dffeas \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y33_N48cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout = ( \u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout &// \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) # ( !\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout & ( (!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout &// (((!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ))) #// (\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout & (!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout & ((\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q )))) ) ).dataa(!\u0|mm_interconnect_0|link_start_s1_agent|rp_valid~combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent|rp_valid~combout ),.datac(!\u0|mm_interconnect_0|link_start_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_demux_007|src0_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207 .lut_mask = 64'h0ACE0ACE00CC00CC;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]).dataa(!\u0|mm_interconnect_0|cmd_mux_016|saved_grant [1]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .lut_mask = 64'h0505050505050505;defparam \u0|mm_interconnect_0|cmd_mux_016|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y33_N20dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_016|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X19_Y33_N26dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y33_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout = (!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0C3F0C3F0C3F0C3F;defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y33_N5dffeas \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y33_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_017|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_017|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_017|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y33_N29dffeas \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_017|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y33_N38dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout = (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) #// (\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ))).dataa(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A5F0A5F0A5F0A5F;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y38_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|always0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF5F5F5F5F0F0F0F0;defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y33_N31dffeas \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y33_N3cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208_combout = ( \u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout &// (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout )))) ) ) # (// !\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout & ((!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ) #// (\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ))) ) ).dataa(!\u0|mm_interconnect_0|data_info_s1_agent|rp_valid~combout ),.datab(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent|rp_valid~combout ),.datac(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~207_combout ),.datad(!\u0|mm_interconnect_0|timecode_tx_ready_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_info_s1_agent_rsp_fifo|mem[0][116]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208 .lut_mask = 64'hF030F030A020A020;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~208 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y24_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y24_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .lut_mask = 64'h00000F0F00000F0F;defparam \u0|mm_interconnect_0|cmd_mux_021|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y24_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_021|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000004040404;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y24_N31dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_021|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y24_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y24_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter// [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y24_N26dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ) #// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0])))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0054005454545454;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y17_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]))).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h10F010F010F010F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y17_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y17_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout & (// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0AFF0AFF555F555F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y17_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .lut_mask = 64'h003F003F00FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y25_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y24_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h00000A0A0000AAAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y23_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00F000F001F501F5;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N41dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N29dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h51BF51BF40AE40AE;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N32dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h4055BFFF4000BFAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N50dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y23_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5]))))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5]))))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h47BB47BB44B844B8;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N26dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y23_N19dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h3055CFFF3000CFAA;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y23_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y23_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ))))// ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )))) )// ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h3310331033503350;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N14dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: FF_X30_Y23_N11dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][76]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h000F000F0000FFFF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N59dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y23_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N17dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y23_N17dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N56dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X30_Y23_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h025702578ADF8ADF;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N54cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y23_N2dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y23_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N8dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N9cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N18cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00CC00CC000C000C;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N20dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N36cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h3210230110320123;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N38dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N48cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N24cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q// )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1040154515451040;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N26dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h1100000011003030;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N32dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N6cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h5151515155555555;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N57cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AF0F0F0F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~0_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h3210103210321032;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N44dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N0cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3FFF3FFFC000C000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N3cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout & (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ) #// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add0~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h0F0A0F0A000A000A;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y25_N5dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y25_N21cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y25_N12cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q &// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y24_N35dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_021|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y25_N29dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N27cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66])) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h505F505F505F505F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y25_N53dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N51cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout &// (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ) # (!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout// )))) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FF00FF00C800C8;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y25_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55FF55FF557F557F;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y25_N41dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y25_N15cyclonev_lcell_comb \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) ) # ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ) ) #// ( \u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) ) # (// !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0F0F0F0FFFFF0F0;defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y24_N55dffeas \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y25_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout = (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .lut_mask = 64'h0033003300330033;defparam \u0|mm_interconnect_0|cmd_mux_020|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y21_N45cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y21_N47dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y21_N39cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (// \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( (\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1] &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout & \u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_020|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_020|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000500050;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y25_N35dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_020|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y25_N44dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y25_N42cyclonev_lcell_comb \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout = (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ))).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A5F0A5F0A5F0A5F;defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y25_N53dffeas \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y29_N14dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y31_N45cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal14~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal14~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal14~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal14~1 .lut_mask = 64'h0F000F0000000000;defparam \u0|mm_interconnect_0|router_001|Equal14~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal14~2 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal14~2_combout = ( \u0|mm_interconnect_0|router_001|Equal14~1_combout & ( \u0|mm_interconnect_0|router_001|Equal1~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~2_combout &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18])) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datae(!\u0|mm_interconnect_0|router_001|Equal14~1_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal14~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal14~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal14~2 .lut_mask = 64'h0000000000000300;defparam \u0|mm_interconnect_0|router_001|Equal14~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y31_N11dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal14~2_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel// [8] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [8]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .lut_mask = 64'h00F000F000FF00FF;defparam \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y27_N58dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router|Equal14~1_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[8] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src8_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [8]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .lut_mask = 64'h3030303033333333;defparam \u0|mm_interconnect_0|cmd_demux|src8_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout = ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout &// (((\u0|mm_interconnect_0|router|Equal7~7_combout & \u0|mm_interconnect_0|router|Equal7~6_combout )))) # (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & (((\u0|mm_interconnect_0|router|Equal7~7_combout &// \u0|mm_interconnect_0|router|Equal7~6_combout )) # (\u0|mm_interconnect_0|router_001|Equal14~2_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|router|Equal14~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & (// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & (// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|router|Equal14~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & (// (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),.datac(!\u0|mm_interconnect_0|router|Equal7~7_combout ),.datad(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datae(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .lut_mask = 64'h111111111111111F;defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout = ( \u0|mm_interconnect_0|router|Equal14~0_combout & ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] &// (\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & \u0|mm_interconnect_0|router|Equal7~7_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.datad(!\u0|mm_interconnect_0|router|Equal7~7_combout ),.datae(!\u0|mm_interconnect_0|router|Equal14~0_combout ),.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .lut_mask = 64'h0000000000000005;defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y30_N11dffeas \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y28_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [34] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & (// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .lut_mask = 64'h00000F0FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N26dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N6cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal14~2_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|cmd_mux_008|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N20dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (// (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] &// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h0CFF0CFF0C0C0C0C;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout )) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h05F505F5F505F505;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N26dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y31_N56dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .lut_mask = 64'h111111111F1F1F1F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $ (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h208A208A75DF75DF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N32dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]// & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]// & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))// # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hFF5FFF5F00A000A0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant// [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) ) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])))) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .lut_mask = 64'hA0A3A0A3A0A3AFAF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] &// \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .lut_mask = 64'h003300330F3F0F3F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N59dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]// & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout )) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~5_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .lut_mask = 64'h05AF05AFAF05AF05;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) #// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hC0CCC0CCC0CCC0CC;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N14dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] = ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( (\u0|hps_0|fpga_interfaces|h2f_WLAST [0]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WLAST [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .lut_mask = 64'h555555555F5F5F5F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_payload[0] .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N32dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h03F303F305F505F5;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FFCC1313FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N2dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &// (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000CCDCCCDC;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h00000000000A000A;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N44dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) )// ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h55BB55BB44AA44AA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N11dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $ (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h23DF23DF20DC20DC;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N26dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])// # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h5111BFFF4000AEEE;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]// & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h00A000A000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N47dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $ (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h1DF31DF30CE20CE2;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y32_N13dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h3505CFFF3000CAFA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h5454545450505050;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h3300330077007700;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout )) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h775577557F5F7F5F;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N8dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .lut_mask = 64'h10FA10FA00AA00AA;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N17dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~14_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h4440444044004400;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & (// (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]))) #// (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ) #// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0])))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000000075307530;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .lut_mask = 64'h000F000F333F333F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( ((\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .lut_mask = 64'h000F000F333F333F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N51cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = (!\u0|mm_interconnect_0|cmd_mux_008|src_data [87] & !\u0|mm_interconnect_0|cmd_mux_008|src_data [88]).dataa(!\u0|mm_interconnect_0|cmd_mux_008|src_data [87]),.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_data [88]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'h8888888888888888;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N53dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y30_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [35] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [3] & (// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N35dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y30_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [32] = ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [0])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .lut_mask = 64'h0F3F0F3F0F3F0F3F;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N59dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [33] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [1] & (// \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N11dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [33]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y30_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|local_write (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout = (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|auto_start_s1_agent|local_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & (// !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .lut_mask = 64'h00000C0C0C0C0000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout &// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .lut_mask = 64'h0A000A00FF00FF00;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F030503050;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N3cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & (// ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .lut_mask = 64'h0303030303FF03FF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N23dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y31_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout = (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout )) )// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout )) )// ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout )// ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) )// ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~7_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .lut_mask = 64'h0055FF55F0550F55;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ) ) # (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout &// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~6_combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~8_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y31_N38dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datag(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "on";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h0C00F0F00C00F5F5;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0011005511115555;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y30_N16dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|src_data [34]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .lut_mask = 64'hC000000080000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .lut_mask = 64'h00000000F0F00000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N21cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q &// ((\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) # (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout & (// (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & (\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout & ((!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]) #// (\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1])))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|read_latency_shift_reg~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .lut_mask = 64'h1101110105550555;defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y30_N59dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y30_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] $// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0000000033CC33CC;defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y30_N44dffeas \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y30_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// ((\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]))) #// (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// ((\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]))) #// (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .lut_mask = 64'h0F4F00004F0F0000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF0F0F0F0FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) #// ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N11dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F0F0000FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y31_N35dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h20A020A030F030F0;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] & ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ) #// ( \u0|mm_interconnect_0|cmd_mux_008|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (((!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q )))) #// (\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_payload [0] & ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & (// (!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & !\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .lut_mask = 64'hAA00BF1500003F3F;defparam \u0|mm_interconnect_0|cmd_mux_008|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y28_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y28_N38dffeas \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N33cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y29_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout = ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout// & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_mux_008|src_payload [0])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// \u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout &// \u0|mm_interconnect_0|cmd_mux_008|src_payload [0])) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & \u0|mm_interconnect_0|cmd_mux_008|src_payload [0])) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout & (// !\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout & !\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_008|packet_in_progress~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_008|src_payload [0]),.datae(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~1_combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_008|src_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .lut_mask = 64'h4444005000500050;defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N41dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y29_N55dffeas \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg~1_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y29_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout = ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout &// \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & ( \u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout &// (\u0|mm_interconnect_0|router_001|Equal14~2_combout & (!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0] & !\u0|mm_interconnect_0|router|Equal14~1_combout ))) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & (// !\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & \u0|mm_interconnect_0|router_001|Equal14~2_combout ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1] & (// !\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout & (\u0|mm_interconnect_0|router_001|Equal14~2_combout & !\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0])) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_demux_001|src8_valid~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal14~2_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [0]),.datad(!\u0|mm_interconnect_0|router|Equal14~1_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_008|arb|top_priority_reg [1]),.dataf(!\u0|mm_interconnect_0|cmd_demux|src8_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .lut_mask = 64'h1010111110001111;defparam \u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N50dffeas \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|arb|grant[1]~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_008|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_008|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y29_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_008|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_008|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_008|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|cmd_mux_008|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y29_N52dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_008|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y29_N12cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]// ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q & ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg// [116] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][116]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h00000F0FF0F0FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N59dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X17_Y32_N50dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][75]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h003300330000FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N59dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y32_N41dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])) # (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// ((!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q & (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][74]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h008833BB44CC77FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N29dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q $// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q $// ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q )))) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00000000D78282D7;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N20dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y32_N32dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4]) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][76]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h030303030000FFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~7_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N17dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y32_N56dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .lut_mask = 64'h1111111100FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~8_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N47dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q &// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3FC0FF003FC0FF00;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [4] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666AAAAAAAA;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q $// (((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ) # (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h00000000A555CCCC;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N50dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [5] ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h78787878F0F0F0F0;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout// & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout// & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3033303330003000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N11dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y32_N59dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N53dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~9_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC0C0000000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter// [3] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout// & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) #// ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0028007D007D0028;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N32dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout// )) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0202000013021100;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N1dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7] & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00F300F300FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )))// ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3131313100000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N8dffeas \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q & (// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q & (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q &// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|burst_uncompress_busy~q ),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y30_N1dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y32_N20dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y32_N35dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ) #// (!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|comb~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FEAAFEAA;defparam \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y29_N17dffeas \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_008|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N48cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q & ((\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ))) ) ) ) # ( \u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0] & ( !\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout & (// (!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ) ) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_translator|waitrequest_reset_override~q ),.datae(!\u0|mm_interconnect_0|auto_start_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .lut_mask = 64'h000000CC0080004C;defparam \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ) # (\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout & (// (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout & ((\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ) #// (\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|nonposted_write_endofpacket~0_combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|m0_read~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h020A020A22AA22AA;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ) # ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout & (// (\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout )))) ) ).dataa(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h00BF00BFFFFFFFFF;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y32_N29dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|always0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|auto_start_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF0FFF0FFF0F0F0F0;defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y29_N4dffeas \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N2dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y23_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y23_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: FF_X27_Y20_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $ (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .lut_mask = 64'h33CC33CC50505050;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .lut_mask = 64'h0F00F0FF11111111;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $ (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [3] & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF30CF30CFF00FF00;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hAAAFAAAF00050005;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [5] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .lut_mask = 64'h0F0FF0F000330033;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N19dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y20_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [6] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]// & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .lut_mask = 64'h5053A0A30003F0F3;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout &// ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~2_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~3_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h4000FFFF0000FFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X30_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFA0A0A0A0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y20_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N49dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) #// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .lut_mask = 64'hC800000000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y20_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1])))) )// ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h00510011FF51FF11;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout )// ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .lut_mask = 64'h0FFF0FFF00000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h00000F0F00000F0F;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) #// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) )// ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h55AF55AF50AA50AA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N14dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h0EF40EF404FE04FE;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N8dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))// # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h4505BFFF4000BAFA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) )// ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h4040404000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y19_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEAE54AE54;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N11dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y19_N25dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] &// ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] &// ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )// # ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) )// ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h3000CFFF3A0ACAFA;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y19_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout// & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'hA000000000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))// ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00FF00FF01030103;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// )))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))))// ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// & \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00F000F004FC04FC;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N5dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )// ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout )))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (((!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout// )))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) )// ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h8888F8888888FFFF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h33003300B380B380;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'h3F3F00003A300000;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y23_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000010101010;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y20_N23dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3 .lut_mask = 64'h44444444C4C4C4C4;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~3_combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0F0A0A00000A0A;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ))) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF00110F1F;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y20_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q &// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h5400540044004400;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #// ((!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0E0F0E0F0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0000FFFFF0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hFF00FF00FC00FC00;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]))) #// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_019|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0101010101FF01FF;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y20_N5dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y20_N17dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y20_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000C000C0C0C0C0C;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0505050500000000;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FFFF0000;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N17dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1] & ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .lut_mask = 64'h000000000000F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0] & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q &// !\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_translator|waitrequest_reset_override~q ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .lut_mask = 64'h0000000055005500;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y20_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF4C4C4C4C;defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y20_N41dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y19_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used// [1] & (((\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h207520752A7F2A7F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1] &// \u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N47dffeas \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000F000F00FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y17_N5dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout &// (\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout &// \u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ))).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0357035703570357;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N11dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0077007700700070;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] &// \u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0])) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y17_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout &// (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] & \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|read~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h0CCF0CCF33FF33FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y17_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y17_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used// [0] ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .lut_mask = 64'h03030F0F0F0F0F0F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout = (\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout & \u0|hps_0|fpga_interfaces|h2f_RREADY [0]).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.datad(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hF3F3F3F3F0F0F0F0;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N35dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y19_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout = (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))// # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q )))).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0437043704370437;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N17dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5410450110540145;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) )// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h3C3C3C3CCCCCCCCC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N23dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N2dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )))) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000E22E00002E2E;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N44dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y19_N56dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used// [1] & (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h003300330C3F0C3F;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N26dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y19_N50dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0303030300FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N53dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q )) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5FFF5FFFA000A000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) )// # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $// (((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout// & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~2_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h00AA00AA00F000F0;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N11dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q )) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ) ) )// ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h1144114405055050;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X30_Y19_N8dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ))) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|Add0~1_combout ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000000040734040;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N38dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: FF_X27_Y19_N41dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ) # ((\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) #// (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000BFBFBFBF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00000000A0AAA0AA;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2] )// ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y19_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q & (// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q & (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q &// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|burst_uncompress_busy~q ),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][78]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y19_N2dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y19_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y19_N50dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y19_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout// )))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent|comb~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFC8FFC8;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y17_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout )) # (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]))) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout &// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0])) ) ) ) # ( \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & (// (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]) ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0303CFCF01016767;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y17_N20dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y23_N59dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y23_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_019|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_019|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_019|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y23_N34dffeas \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_019|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y23_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]// & \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y25_N32dffeas \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y17_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0] &// ((!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fsm_info_s1_translator|read_latency_shift_reg [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .lut_mask = 64'hE0E0E0E000000000;defparam \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y25_N30cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209_combout = ( \u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( (!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout & (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout &// \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q )) ) ) # ( !\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout & ( ((!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout &// (!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout & \u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ))) # (\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|rsp_demux_008|src0_valid~0_combout ),.datab(!\u0|mm_interconnect_0|auto_start_s1_agent|rp_valid~combout ),.datac(!\u0|mm_interconnect_0|auto_start_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(!\u0|mm_interconnect_0|fsm_info_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fsm_info_s1_agent|rp_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209 .lut_mask = 64'h08FF08FF08080808;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y25_N51cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210_combout = ( !\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209_combout & ( (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout &// (!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q & ((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout )))) #// (\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout & (((!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q )) # (\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ))) ) ).dataa(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent|rp_valid~combout ),.datab(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent|rp_valid~combout ),.datac(!\u0|mm_interconnect_0|counter_rx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(!\u0|mm_interconnect_0|counter_tx_fifo_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~209_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210 .lut_mask = 64'hF351F35100000000;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~210 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X30_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal18~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [19] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal18~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal18~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal18~0 .lut_mask = 64'h00000000FFFF0000;defparam \u0|mm_interconnect_0|router_001|Equal18~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal18~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal18~1_combout = ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &// (\u0|mm_interconnect_0|router_001|Equal1~2_combout & \u0|mm_interconnect_0|router_001|Equal18~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal18~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal18~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal18~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal18~1 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|router_001|Equal18~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N37dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal18~1_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[12] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ( (\u0|mm_interconnect_0|router_001|Equal18~1_combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [12]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|mm_interconnect_0|router_001|Equal18~1_combout ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .lut_mask = 64'h0000000000F500F5;defparam \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1].dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hF0F0F0F0F0F0F0F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000005000500;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y34_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFF2A2A2A2A;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FFFF00035557;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000A000A0A0A0A0A;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X4_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout $// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h33CC33CC30FC30FC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h30CF30CF22EE22EE;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h3202CEFE0202FEFE;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0C000C0000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0FF00FF022EE22EE;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N38dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N13dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h5050AFAF3300FFCC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0000F4F40404F4F4;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N35dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00CC00CC01CF01CF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'hAAAAAAAA00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y34_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0C0C0C0C000C000C;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h1BB11BB10AA00AA0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X4_Y34_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X4_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]// & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .lut_mask = 64'h4040B0B0404FB0BF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X4_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X4_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X4_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hBB44BB44FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) )// ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .lut_mask = 64'hF1F1F1F101010101;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h4400440000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h01AB01ABAB01AB01;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X4_Y34_N37dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X4_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X4_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) ) )// ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h00C0F03005C5F535;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X4_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout & (// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~3_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2F0F0F0F0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X4_Y34_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: FF_X8_Y34_N23dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X8_Y34_N59dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X8_Y34_N55dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .lut_mask = 64'hA0000000A0000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFC0C0C0C0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N35dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~1_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .lut_mask = 64'h50F050F000F000F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0F0A0F0A000A000A;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]) # (((!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout// )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hFFFBFFFB00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout &// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y34_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )// # ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q// & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h02030003F2F3F0F3;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .lut_mask = 64'hCCCCCCCCC0C0C0C0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h11111111111F111F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y34_N14dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X7_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: FF_X7_Y34_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0030003030303030;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000050505050;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N14dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000000000C0C0C0C;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h050F050F00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .lut_mask = 64'h44444444E444E444;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .lut_mask = 64'hAA08AA8800000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .lut_mask = 64'hE000E000A000A000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .lut_mask = 64'h00FF00FF05AF05AF;defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N29dffeas \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_012|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~4_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_012|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .lut_mask = 64'hFF00FF00FC0CFC0C;defparam \u0|mm_interconnect_0|cmd_mux_012|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N35dffeas \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_012|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_012|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_012|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N5dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &// ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]// & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .lut_mask = 64'h8080000080000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h000000000FFF0FFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N8dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h003300330F3F0F3F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout )))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55F755F755FF55FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N8dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000C0C0C0C;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y34_N29dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) # (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0000555055505550;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg// [0] & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]// & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N35dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N23dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N53dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N2dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h083B083B4C7F4C7F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N41dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N14dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N29dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h005500550000FFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N17dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X6_Y34_N5dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00F000F000300030;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N8dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5404510104540151;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N2dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout = !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $// (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]))).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h7878787878787878;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q $ (((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ))))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0000D87200007272;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N26dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3030303033003300;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N59dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000202011003120;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N20dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h4545454555555555;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q// )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ))// # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q// )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0028007D007D0028;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y33_N44dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y33_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q & \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0080000000000000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N38dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00330033CCFFCCFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N50dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout & (// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) # (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|comb~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FFEEFF00;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y33_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]))) #// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y33_N11dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y31_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_012|saved_grant [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_012|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|cmd_mux_012|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y31_N52dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_012|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y31_N32dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout = (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ))).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A5F0A5F0A5F0A5F;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem~20_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y31_N1dffeas \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y33_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .lut_mask = 64'hAA00AA00A000A000;defparam \u0|mm_interconnect_0|fifo_full_tx_status_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N36cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal3~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal3~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal3~0 .lut_mask = 64'h0F000F0000000000;defparam \u0|mm_interconnect_0|router_001|Equal3~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal11~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal11~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|mm_interconnect_0|router_001|Equal1~0_combout &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal3~0_combout ))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal11~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal11~0 .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|router_001|Equal11~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y31_N16dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|Equal11~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal11~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [6]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal11~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .lut_mask = 64'h0000000000F300F3;defparam \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y36_N56dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y37_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hFFFF0000FFFF0000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y37_N26dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N2dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000F000F00000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N47dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y37_N50dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y37_N14dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y37_N8dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]// & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N46dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y37_N11dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0555055500000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N23dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ))).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0C5D0C5D0C5D0C5D;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) #// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFAAFFAAFF0AFF0A;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N41dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .lut_mask = 64'h35C535C530C030C0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N14dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout// & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1])) ) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout// & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h00C005C5F030F535;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N32dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hF30CF30CFF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .lut_mask = 64'hAAAFAAAF00050005;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N47dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ) #// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h01F101F1F101F101;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N38dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y37_N2dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) #// ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ) ) ) ) #// ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )// # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .lut_mask = 64'h3030CFCF00550055;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~2_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h0000FFFF8000FFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N26dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: FF_X17_Y37_N55dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F05AF0F0F0D2F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hF000F000FF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout =// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h32DC32DC32DC32DC;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N17dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h0EF40EF404FE04FE;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N50dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h0000FFFFE4444EEE;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N8dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEAE54AE54;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N53dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N19dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h000CFFFCA0AC5F5C;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00CC00CC10FC10FC;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N56dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h02EE02EE00CC00CC;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N2dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N35dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h083B083B4C7F4C7F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N47dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y37_N41dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N59dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F505F505F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N23dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N29dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N20dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N32dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q )))).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0437043704370437;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N53dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y37_N26dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y37_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N29dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h5AAA5AAAAAAAAAAA;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h5044501105440511;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N14dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h66666666CCCCCCCC;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout// ) # (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h5044004405445544;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N32dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3FC03FC0FF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N59dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'h8080808000000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q// $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $ (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout// )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q $// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N2dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h00000088000030B8;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N37dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout = (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]))).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h3303330333333333;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h0C0F0C0F00000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y37_N8dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y37_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y37_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000000080000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N50dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h000F000FF0FFF0FF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N20dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) #// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000FEF0FEF0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y36_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h00000000CFCFCFCF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y37_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & ( ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000FF3FFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y37_N41dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y37_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] )// ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCFCFCFCFCCCCCCCC;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y36_N41dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .lut_mask = 64'h000000007F7F7F7F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y37_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout// & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h00AF00AF23732373;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y37_N56dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3 .lut_mask = 64'h3F333F3300000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout ))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|cp_ready~3_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00AF00AF00A000A0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001FF01;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N38dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0F080F0800000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # ((!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0E0F0E0F0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y37_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N32dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout )) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F1F0F1F00110011;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N29dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0C3FAAAF00FFAAAF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout &// ( \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .lut_mask = 64'h00FF00FF0CFC0CFC;defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N55dffeas \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_006|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout = (!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & (((!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q )))) # (\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] &// ((!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout & ((!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout &// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )))).dataa(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_006|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .lut_mask = 64'hF0B1F0B1F0B1F0B1;defparam \u0|mm_interconnect_0|cmd_mux_006|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N26dffeas \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_006|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_006|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y37_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFC0C0FFFFC0C0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y37_N20dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y37_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # (// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]// ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q// & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [3]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'h1FFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000003030303;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y36_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N53dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N8dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|wait_latency_counter [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000C0C0C0C;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N38dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y36_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])))) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0707070707000700;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg// [0] & \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N41dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y36_N45cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] &// ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ) ) # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h5050FFFF0F0F5F5F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y36_N47dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_006|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_006|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|cmd_mux_006|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y36_N14dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_006|src_payload~11_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y36_N44dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q & (// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q & ( (!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0A0A0A0A5F5F5F5F;defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y36_N37dffeas \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout = ( \u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q &// (((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q )) # (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) )// # ( !\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q & ((\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.datad(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_empty_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .lut_mask = 64'h050F050F070F070F;defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~57 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y31_N33cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal9~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal9~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal7~0_combout & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|mm_interconnect_0|router_001|Equal7~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal9~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal9~0 .lut_mask = 64'h0000000000000004;defparam \u0|mm_interconnect_0|router_001|Equal9~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y31_N34dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal9~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal9~0_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal9~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .lut_mask = 64'h000000000A0F0A0F;defparam \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N38dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N41dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N50dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y34_N47dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) # (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFF0FFF0FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N2dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X9_Y34_N11dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q// & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [3])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .lut_mask = 64'h7F7F7FFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N14dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|waitrequest_reset_override~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .lut_mask = 64'h000F000F00000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ) # (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFF3FFF3FF00FF00;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y36_N23dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N17dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y36_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .lut_mask = 64'h10BA10BABA10BA10;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y36_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))// ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h00A0F05003A3F353;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y36_N8dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y36_N50dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y36_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [4] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hFF77FF7700880088;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y36_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout// & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) )// ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .lut_mask = 64'hF1F1F1F101010101;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y36_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h0808080800000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y36_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y36_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout &// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .lut_mask = 64'h0AA00AA01BB11BB1;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y36_N19dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y36_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) )// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) )// # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h5053A0A30003F0F3;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y36_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~3_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h4000FFFF0000FFFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y36_N26dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]// & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))// ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .lut_mask = 64'hC000000000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1].dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y34_N2dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~2_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00EA002A00FF0000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N4dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q// ))) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// ((((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F551D0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) # ((\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]))) ) )// ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & ( (\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1])) ) )// ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0000FAFA0003FAFB;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N20dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .lut_mask = 64'hFF00FF000F000F00;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFFA50FA50;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N23dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y34_N20dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .lut_mask = 64'h00FF00FFE44EE44E;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout )) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .lut_mask = 64'h00ACFF5C000CFFFC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N38dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N43dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h04FE04FEF40EF40E;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .lut_mask = 64'h5350AFAC0300FFFC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~1_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~4_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~2_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h0022EEEE0000CCCC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h01DD01DD00CC00CC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y34_N26dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q// & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h2220222022002200;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ( !\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.dataf(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hAAAAAAAAAAAA88AA;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout &// ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h55FF55FF00AA00AA;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N5dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h01FF01FF01010101;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N26dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0C00AAAA3FFFAFAF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y34_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout & (// \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .lut_mask = 64'h00FF00FF0CFC0CFC;defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N47dffeas \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_005|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q )// # ((\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] & \u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout )) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &// ( (!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q & ((!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]) # (!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_005|packet_in_progress~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .lut_mask = 64'hCCC0CCC0CCCFCCCF;defparam \u0|mm_interconnect_0|cmd_mux_005|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y34_N14dffeas \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_005|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_005|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y34_N8dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h000000000C0CCCCC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0F0F0F0F000F000F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N38dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q )) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h333F333F000F000F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hAAAAAAAAFFAAFFAA;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N14dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N21cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|wait_latency_counter [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000050505050;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N23dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0])))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h000000003F2A3F2A;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg// [0] & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]// & \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N35dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .lut_mask = 64'h030F030F0F0F0F0F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N29dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N27cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N8dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y34_N59dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N57cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N14dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y34_N50dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N29dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X14_Y34_N26dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N11dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X13_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][74]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h05330533AF33AF33;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N5dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0000800000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h0000000033333333;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout = !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q )))).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h6CCC6CCC6CCC6CCC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h3CCC3CCCCCCCCCCC;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h5050505055005500;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N41dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N15cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q// )))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ))// # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q// )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0408070B070B0408;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N44dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N48cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000080800005D08;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N50dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N12cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000F7F7F7F7;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3000300033003300;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) ) # ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h2121212133000033;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h7777777788888888;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y34_N18cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h5044054405440544;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y34_N20dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y34_N33cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3])) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y34_N32dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y34_N30cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h00330033CCFFCCFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N8dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ) #// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout & ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ) #// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|comb~0_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~1_combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][66]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00000000EEEAEEEA;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y34_N51cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] &// ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) )// ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33FF33FF337F337F;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N53dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]))))) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout & ((\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h4747474711471147;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y34_N56dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y32_N11dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] & ( \u0|mm_interconnect_0|cmd_mux_005|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_005|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .lut_mask = 64'h0000000055555555;defparam \u0|mm_interconnect_0|cmd_mux_005|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y32_N14dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_005|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]) # (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] & ( (\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h00550055AAFFAAFF;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y32_N37dffeas \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y30_N38dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hF0FFF0FFF0FFF0FF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (// (\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .lut_mask = 64'hFF00FF000F000F00;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y30_N56dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[87] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [87] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .lut_mask = 64'h0303030357575757;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[87] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[88] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [88] = ( \u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_AWSIZE [2]),.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .lut_mask = 64'h0505050505FF05FF;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[88] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [88] & ( !\u0|mm_interconnect_0|cmd_mux_004|src_data [87] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|src_data [87]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|src_data [88]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hF0F0F0F000000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y30_N38dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[34] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [34] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [2] & (// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .lut_mask = 64'h00FF00FF0FFF0FFF;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[34] .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N56dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [34]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[35] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [35] = ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|hps_0|fpga_interfaces|h2f_WSTRB [3])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datad(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [3]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .lut_mask = 64'h0F5F0F5F0F5F0F5F;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[35] .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N47dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [35]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y28_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) #// ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .lut_mask = 64'h00000F0FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y28_N56dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [32]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y28_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[33] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [33] = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [1] ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .lut_mask = 64'h00000F0FFFFFFFFF;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[33] .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N11dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_004|src_data [33]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .lut_mask = 64'h8000800080008000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter// [0] $ (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0000000055AA55AA;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N17dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y30_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y30_N20dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]// & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1])) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .lut_mask = 64'h8800000080000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .lut_mask = 64'h0C0C0C0C00000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0])// # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1])))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .lut_mask = 64'h000B000B00770077;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter// [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0]~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N23dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q )) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .lut_mask = 64'h0044004400880088;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y30_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~1_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .lut_mask = 64'h00A000A0AAAAAAAA;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & (// (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &// !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[74]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .lut_mask = 64'h7755775533003300;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N53dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N8dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y30_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout )) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h05AF05AFAF05AF05;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N50dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y30_N15cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & (// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[75]~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h005500550F5F0F5F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] $// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]// $ (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h208A208A75DF75DF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & (// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[78]~4_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout )) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[77]~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hDD22DD22FF00FF00;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ))) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_cp_data[76]~1_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F3F5F700030507;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N2dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y30_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2] & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h2200220000000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~7_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .lut_mask = 64'h05AF05AFAF05AF05;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N23dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y30_N32dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y30_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] $// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6])))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q// & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~5_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .lut_mask = 64'h11BB11BBB11BB11B;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~6_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~8_combout ),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h40000000FFFFFFFF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N56dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ) )// ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout &// ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]))) ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .lut_mask = 64'h0000FFFF1313FF33;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N8dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~15_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'h00000000F8F8F8F8;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ))) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (// (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0] & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h0022303300000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y30_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) # ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~3_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'hFF47FF4700000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y30_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout &// ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0F0FFFFF0000F0F0;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y30_N29dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h7000700077007700;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h003F003F00000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N2dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [68]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout $// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0])))) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .lut_mask = 64'h00004800FF00FF00;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout =// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000F000F000F000F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout =// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .lut_mask = 64'h54AE54AE54AE54AE;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N5dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] $// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h50AF50AF44EE44EE;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N44dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X28_Y32_N56dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) ) ) ) # (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .lut_mask = 64'h5000AFFF4444EEEE;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] &// ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N47dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout $// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .lut_mask = 64'h0FF00FF044EE44EE;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N13dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X28_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout = (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) #// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))// ) ) ) # ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ))))// # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .lut_mask = 64'h0F44F0EE0044FFEE;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout = (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout &// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~4_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~5_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h00000000F0F4F0F4;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q// & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) )// ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h3330333033003300;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N12cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout = ( !\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// \u0|mm_interconnect_0|cmd_mux_004|saved_grant [0])) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_demux|src4_valid~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .lut_mask = 64'h0000000001010000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ))) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h3030303030F030F0;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & (// (((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout )) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ) ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout & ( ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout &// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideOr0~combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~12_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .lut_mask = 64'h33F333F377F777F7;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y32_N32dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~13_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q// & (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ))))) ) ) # (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ))))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~0_combout ),.datag(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .extended_lut = "on";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .lut_mask = 64'h0A00F0F00A00F3F3;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout = ( !\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .lut_mask = 64'hFFFFFFFF00000000;defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N32dffeas \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_004|packet_in_progress .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y30_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & ( !\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ) ) # ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (// (\u0|mm_interconnect_0|cmd_mux_004|src_payload [0] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ))) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|src_payload [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~1_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_004|packet_in_progress~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .lut_mask = 64'h11551155F0F0F0F0;defparam \u0|mm_interconnect_0|cmd_mux_004|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N26dffeas \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|arb|grant[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|cmd_mux_004|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_004|saved_grant[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y31_N54cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout = ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( \u0|mm_interconnect_0|router_001|Equal7~1_combout & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] &// (\u0|mm_interconnect_0|router_001|Equal1~1_combout & (\u0|mm_interconnect_0|router_001|Equal1~0_combout & \u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_demux_001|src4_valid~0_combout ),.datae(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal7~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .lut_mask = 64'h0000000000000001;defparam \u0|mm_interconnect_0|cmd_mux_004|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y27_N21cyclonev_lcell_comb \u0|mm_interconnect_0|router|Equal7~10 (// Equation(s):// \u0|mm_interconnect_0|router|Equal7~10_combout = ( \u0|mm_interconnect_0|router|Equal7~9_combout & ( (\u0|mm_interconnect_0|router|Equal7~6_combout & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|Equal7~9_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|Equal7~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|Equal7~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|Equal7~10 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|router|Equal7~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y27_N4dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router|Equal7~10_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y27_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src4_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ) ) # (// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4] & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [4]),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .lut_mask = 64'h00000000F0F0FFFF;defparam \u0|mm_interconnect_0|cmd_demux|src4_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y30_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|WideOr1 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout = ( !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout & ( \u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout & ( (!\u0|mm_interconnect_0|router|Equal7~6_combout ) #// ((!\u0|mm_interconnect_0|router|Equal7~9_combout ) # ((!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) # (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout & ( !\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ) ).dataa(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datab(!\u0|mm_interconnect_0|router|Equal7~9_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),.datae(!\u0|mm_interconnect_0|cmd_mux_004|src_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux|src4_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .lut_mask = 64'hFFFF0000FFFE0000;defparam \u0|mm_interconnect_0|cmd_mux_004|WideOr1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout = ( !\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_004|WideOr1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .lut_mask = 64'h0F0F0F0F00000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y30_N45cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout )// ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_valid~combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F0F0F0FFF0FFF0F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X27_Y30_N47dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: FF_X23_Y30_N23dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X23_Y30_N29dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y30_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .lut_mask = 64'h000F000F0F0F0F0F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout &// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h4444444400000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N0cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q & (((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1])) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0] & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1] & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout &// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|waitrequest_reset_override~q ),.datae(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [0]),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .lut_mask = 64'h000800F700000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y32_N53dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|local_write~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X25_Y30_N29dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y30_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q )))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout )) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h0C3F0C3F4C7F4C7F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) #// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hCCCCCCCCFCFCFCFC;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y32_N44dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) #// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ))).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'hAB03AB03AB03AB03;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout &// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0])) # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .lut_mask = 64'h0C3F0C3F00000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h05FF05FF00000000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y32_N26dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout & (// ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|read~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h50FF50FF0F5F0F5F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y32_N38dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .lut_mask = 64'h1313131333333333;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]))// # (\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout & ((\u0|hps_0|fpga_interfaces|h2f_BREADY [0]))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(!\u0|hps_0|fpga_interfaces|h2f_BREADY [0]),.datac(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h0000000053535353;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X25_Y30_N18cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ))) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout & (// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout & (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout )))) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|m0_read~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|cp_ready~4_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|nonposted_write_endofpacket~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h044404440CCC0CCC;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ) )// ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|always0~0_combout ),.datab(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h33BF33BF33FF33FF;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X23_Y32_N8dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X23_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] &// (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0])) ) ) # ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .lut_mask = 64'hAA00AA00A000A000;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y34_N3cyclonev_lcell_comb \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout = ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ) ) ) ) # ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0] & (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0] ) ) ).dataa(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rdata_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][129]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_translator|read_latency_shift_reg [0]),.dataf(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .lut_mask = 64'hAAAA0000A0A00000;defparam \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y29_N33cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_004|src_data[116] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_004|src_data [116] = ( \u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( ((\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11])) # (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_AWID [11] & ( (\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1] & \u0|hps_0|fpga_interfaces|h2f_ARID [11]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [1]),.datab(!\u0|mm_interconnect_0|cmd_mux_004|saved_grant [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datad(gnd),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_AWID [11]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .lut_mask = 64'h0505050537373737;defparam \u0|mm_interconnect_0|cmd_mux_004|src_data[116] .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y29_N35dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_004|src_data [116]),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y32_N59dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 (// Equation(s):// \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout = (!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// (\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116])) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ))).dataa(!\u0|mm_interconnect_0|data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datab(gnd),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .extended_lut = "off";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .lut_mask = 64'h505F505F505F505F;defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y32_N32dffeas \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem~21_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215_combout = ( \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q & (// (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ))) ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( \u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout &// (!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q & ((\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ) # (\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout )))) ) ) ) # (// \u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( !\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ) ) ) # (// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout & ( !\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q & ( (!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout &// !\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ) ) ) ).dataa(!\u0|mm_interconnect_0|rsp_mux_001|src_payload~57_combout ),.datab(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][116]~q ),.datac(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent|rp_valid~combout ),.datad(!\u0|mm_interconnect_0|rsp_demux_004|src0_valid~0_combout ),.datae(!\u0|mm_interconnect_0|fifo_full_rx_status_s1_agent|rp_valid~combout ),.dataf(!\u0|mm_interconnect_0|data_read_en_rx_s1_agent_rsp_fifo|mem[0][116]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215 .lut_mask = 64'h8888AAAA08880AAA;defparam \u0|mm_interconnect_0|rsp_mux_001|src_data[116]~215 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y31_N15cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~4 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~4_combout = ( \u0|mm_interconnect_0|router_001|Equal1~1_combout & ( \u0|mm_interconnect_0|router_001|Equal1~2_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]// & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & \u0|mm_interconnect_0|router_001|Equal1~0_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.datad(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datae(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~4 .lut_mask = 64'h0000000000000008;defparam \u0|mm_interconnect_0|router_001|Equal1~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y31_N57cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal1~5 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal1~5_combout = (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & \u0|mm_interconnect_0|router_001|Equal1~4_combout ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal1~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal1~5 .lut_mask = 64'h2222222222222222;defparam \u0|mm_interconnect_0|router_001|Equal1~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N58dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|router_001|Equal1~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout &// \u0|hps_0|fpga_interfaces|h2f_ARVALID [0])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (\u0|mm_interconnect_0|router_001|Equal1~4_combout &// (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|mm_interconnect_0|router_001|Equal1~4_combout ),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .lut_mask = 64'h0200020002020202;defparam \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y35_N59dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1].dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hCCCCCCCCCCCCCCCC;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout &// \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000030003;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000AA00AA;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1] &// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000000F000F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N23dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ).dataa(gnd),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFC0C0C0C0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y32_N2dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: FF_X9_Y35_N50dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y35_N17dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y35_N53dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X9_Y35_N26dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & ( (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3])) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .lut_mask = 64'h1FFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h0C0C0C0C0CFF0CFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFFFFFFFF0C0C0C0C;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N50dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & (\u0|hps_0|fpga_interfaces|h2f_RREADY [0]// & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h030F030F020A020A;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X22_Y18_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h00F000F030F030F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y18_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X22_Y18_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & ( ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout & (// ((\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1])) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h30FF30FF0F3F0F3F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X22_Y18_N47dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .lut_mask = 64'h050F050F0F0F0F0F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) # ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFCF0FCF0FFF0FFF0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N55dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .lut_mask = 64'hF0F0F0F030303030;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y32_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~1_combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]// $ (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) #// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .lut_mask = 64'h00FF00FFE44EE44E;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) #// ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .lut_mask = 64'h5404AEFE0404FEFE;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h5000500000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .lut_mask = 64'h04FE04FEF40EF40E;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N31dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [5])))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) )// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .lut_mask = 64'h0404FEFEF4040EFE;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X8_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~4_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~2_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .lut_mask = 64'h0F0FF0F044444444;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]// & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]) ) )// ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .lut_mask = 64'h3030CFCF00550055;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N26dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg// [4] $ (((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'hDD22DD22FF00FF00;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout &// ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .lut_mask = 64'hF0F5F0F500050005;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N23dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'h3000300000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .lut_mask = 64'h0FF00FF011111111;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]// & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]) ) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ) #// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .lut_mask = 64'h5500AAFF03030303;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X6_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~3_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~2_combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h2000FFFF0000FFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X6_Y35_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: FF_X9_Y35_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ))) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] &// ((((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F330F0F0F1B0F;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h5750575050505050;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) )// ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// )))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h01DD01DD00CC00CC;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N47dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [2]))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFEE44EE44;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y35_N23dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X8_Y32_N56dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h5353535300FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N29dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X8_Y32_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y32_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y32_N41dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q// $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q// $ (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00C300C300AA0055;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N50dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y32_N11dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N14dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q// ))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q &// ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q// & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ))) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h0E04040E040E040E;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: FF_X8_Y32_N38dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h0505050500FF00FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N26dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hC000C00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X8_Y32_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X8_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [6]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][78]~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h050505050000FFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N59dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q & !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q & (// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3FFF3FFFC000C000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3030303033003300;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) )// # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout $// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout// & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) )// ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0440155115510440;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q &// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0000404000004F40;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N31dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X7_Y32_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000DFDFDFDF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q// & !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout )) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h3000300033003300;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X7_Y32_N20dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y32_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X7_Y32_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q & (// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q &// !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h4000000000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N47dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout = (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))// # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ))).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[1][66]~q ),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h303F303F303F303F;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N56dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X6_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout & \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout & (// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][66]~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|comb~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h0F0F0F0F0C0C0808;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y32_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1])))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout &// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout & ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout &// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])))) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout &// ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h05AF05AF01670167;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N32dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0])) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3 .lut_mask = 64'h0A000A00AAAAAAAA;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~3_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h00AF00AF00A000A0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q &// ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001FF01;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h00000000F800F800;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (// (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout )))) ) ) # (// !\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0E0F0E0F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h00FF00FFF0F0F0F0;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N44dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1])) ) ) # (// !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( ((\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout &// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]))) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0F1F0F1F00110011;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q )) #// (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout// ))))) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ) # (// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) #// (((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datag(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h0C00AAAA3FFFAFAF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y31_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ((\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .lut_mask = 64'h00FF00FF22EE22EE;defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N29dffeas \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_001|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y31_N24cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & ((!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ))) #// (\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] & (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datac(!\u0|mm_interconnect_0|cmd_mux_001|packet_in_progress~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .lut_mask = 64'hF0F0F0F0D1D1D1D1;defparam \u0|mm_interconnect_0|cmd_mux_001|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N44dffeas \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|last_cycle~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_001|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_001|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder_combout = ( \u0|mm_interconnect_0|cmd_mux_001|saved_grant [1] ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder .lut_mask = 64'h00000000FFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y35_N52dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X10_Y32_N5dffeas \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_001|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X10_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ((\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]) # (\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h050F050F00000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y32_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N8dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000005050505;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y32_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout = (\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout & !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h0F000F000F000F00;defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N29dffeas \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_translator|waitrequest_reset_override~q ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .lut_mask = 64'h0505050500000000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y32_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout &// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|cp_ready~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem~0_combout ),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0F0F0F0F03030303;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X9_Y32_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1] & ( ((\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] &// ((!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ) # (\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout )))) # (\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|write~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent|uncompressor|always0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h55F755F755FF55FF;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X9_Y32_N35dffeas \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X9_Y32_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid (// Equation(s):// \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout = ( \u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & ( (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0] &// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0])) ) ) # ( !\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q & (// (!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0] & !\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]) ) ).dataa(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem_used [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_rx_s1_translator|read_latency_shift_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .lut_mask = 64'hF000F000A000A000;defparam \u0|mm_interconnect_0|timecode_rx_s1_agent|rp_valid .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y31_N6cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_channel[2]~0 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & !\u0|mm_interconnect_0|router_001|Equal2~1_combout ))) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datad(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .lut_mask = 64'h0000000040000000;defparam \u0|mm_interconnect_0|router_001|src_channel[2]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y31_N14dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[2] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout = ( \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout & ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) ) # (// \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout & ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2] & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &// !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datae(!\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .lut_mask = 64'h00000F0000000F0F;defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N23dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] & \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .lut_mask = 64'h0000000000CC00CC;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N14dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .lut_mask = 64'h000F000F00000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N59dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2]~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y34_N8dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y34_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]))) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARLEN [0] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] $// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARLEN [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .lut_mask = 64'h35C535C530C030C0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y34_N44dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y34_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2])))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ))) ) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) #// ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~3_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .lut_mask = 64'h0101F1F1F10101F1;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N5dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: MLABCELL_X25_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2] & ( \u0|hps_0|fpga_interfaces|h2f_ARVALID [0] ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel// [2] & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q & \u0|hps_0|fpga_interfaces|h2f_ARVALID [0]) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(gnd),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .lut_mask = 64'h0A0A0F0F0A0A0F0F;defparam \u0|mm_interconnect_0|cmd_demux_001|src2_valid~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & \u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~1_combout ),.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datad(!\u0|mm_interconnect_0|router_001|src_channel[2]~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .lut_mask = 64'h0000000000010001;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N29dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[2] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y35_N41dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y35_N8dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y35_N56dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1] &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .lut_mask = 64'h8000800000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout = !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1].dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y35_N5dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .lut_mask = 64'h0FFF0FFF00F000F0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N44dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~8_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q// & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]))) ) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q &// ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ) # ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~2_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .lut_mask = 64'h0000F4FC0000B030;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) #// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ))) ) ) ) #// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout// ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .lut_mask = 64'h0001FFFF0001CCCD;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N8dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .lut_mask = 64'hBBBBBBBB00000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~1_combout ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .lut_mask = 64'h00FF00FFEE44EE44;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y35_N41dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] $// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]))))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .lut_mask = 64'h00FF00FFAC5CAC5C;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y35_N26dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ) #// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2]))))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .lut_mask = 64'h2320DFDC0300FFFC;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y35_N56dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y35_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg// [3] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2] &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4])) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .lut_mask = 64'h0A000A0000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5])))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg// [2])) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] $// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .lut_mask = 64'h0AF50AF54EE44EE4;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X17_Y35_N38dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] .power_up = "low";// synopsys translate_on// Location: FF_X17_Y35_N20dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X17_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q & (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2])))) ) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q// )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout// & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add4~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .lut_mask = 64'h2020DFDF2F20DFD0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X17_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout = (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6]~1_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2]~5_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[4]~3_combout ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[5]~2_combout ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[3]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .lut_mask = 64'h8080000000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .lut_mask = 64'h332A332A33003300;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N41dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~10_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor1~combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .lut_mask = 64'h00AA00AA10FA10FA;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N32dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state~9_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N22dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )// ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q )) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) )// ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .lut_mask = 64'h4444404044440000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N51cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout &// ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) #// (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout &// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~1_combout ),.datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .lut_mask = 64'hF0F0F0F0F0A0F0F0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y34_N41dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y34_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]// & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] $// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .lut_mask = 64'hC3F0C3F0F0F0F0F0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y34_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout )) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .lut_mask = 64'hFF05FF0500050005;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y34_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4] &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2] &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3])) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [4]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [3]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .lut_mask = 64'h00000000C000C000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y34_N56dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y34_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout = ( \u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout $// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5])))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) # ( !\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout $// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .lut_mask = 64'h0AA00AA01BB11BB1;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y34_N25dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y34_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ) # ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) ) #// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & ( (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) ) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])))) ) ) ) #// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q & (((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Add1~1_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|Add2~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [6]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .lut_mask = 64'h5053A0A30003F0F3;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y34_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout = (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout & (// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[2]~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[3]~3_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|Selector1~2_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[4]~1_combout ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[6]~4_combout ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_bytes_remaining[5]~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .lut_mask = 64'h4F0F0F0F0F0F0F0F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y34_N2dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout = (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q )))// ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))))) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_eop_reg~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .lut_mask = 64'h0F0F470F0F0F4747;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ) )// ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ) ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_eop~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.datae(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .lut_mask = 64'h0C0C0C0C0C0C0CFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y35_N11dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_out_valid~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q// & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .lut_mask = 64'hFFFFFFFFBB00BB00;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X18_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout = (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ))))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout )) ) ) # (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q & ( ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q )// # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q )))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd~combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS~q ),.datag(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .extended_lut = "on";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .lut_mask = 64'h1D1DFF055555FF05;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( (\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q// & ((!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ) # (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout & ( ((\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1])) #// (\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datad(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .lut_mask = 64'h03FF03FF00FC00FC;defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N49dffeas \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_002|packet_in_progress .power_up = "low";// synopsys translate_on// Location: MLABCELL_X19_Y31_N0cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|src_data[103]~5 (// Equation(s):// \u0|mm_interconnect_0|router_001|src_data[103]~5_combout = ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] &// (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]))) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19] & ((!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])))) ) ) ) # (// !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & ( \u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]))) #// (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17] & (!\u0|mm_interconnect_0|router_001|Equal2~1_combout & (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [19])))) ) ) ) # ( \u0|hps_0|fpga_interfaces|h2f_ARADDR [16] & (// !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # (!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] $ (\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]// & ( !\u0|mm_interconnect_0|router_001|Equal1~3_combout & ( (!\u0|mm_interconnect_0|router_001|Equal2~1_combout ) # ((!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & !\u0|hps_0|fpga_interfaces|h2f_ARADDR [17])) ) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datab(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [19]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [17]),.datad(!\u0|mm_interconnect_0|router_001|Equal2~1_combout ),.datae(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [16]),.dataf(!\u0|mm_interconnect_0|router_001|Equal1~3_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|src_data[103]~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .lut_mask = 64'hFFA0FFA589809181;defparam \u0|mm_interconnect_0|router_001|src_data[103]~5 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X23_Y31_N42cyclonev_lcell_comb \u0|mm_interconnect_0|router_001|Equal3~1 (// Equation(s):// \u0|mm_interconnect_0|router_001|Equal3~1_combout = ( !\u0|hps_0|fpga_interfaces|h2f_ARADDR [18] & ( (\u0|mm_interconnect_0|router_001|Equal1~0_combout & (\u0|mm_interconnect_0|router_001|Equal1~1_combout &// (\u0|mm_interconnect_0|router_001|Equal3~0_combout & \u0|mm_interconnect_0|router_001|Equal1~2_combout ))) ) ).dataa(!\u0|mm_interconnect_0|router_001|Equal1~0_combout ),.datab(!\u0|mm_interconnect_0|router_001|Equal1~1_combout ),.datac(!\u0|mm_interconnect_0|router_001|Equal3~0_combout ),.datad(!\u0|mm_interconnect_0|router_001|Equal1~2_combout ),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_ARADDR [18]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router_001|Equal3~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router_001|Equal3~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|router_001|Equal3~1 .lut_mask = 64'h0001000100000000;defparam \u0|mm_interconnect_0|router_001|Equal3~1 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y31_N30cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout = ( \u0|mm_interconnect_0|router_001|Equal3~1_combout & ( (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] & (\u0|mm_interconnect_0|router_001|src_data[103]~5_combout &// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2])))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [2]),.datac(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datad(!\u0|mm_interconnect_0|router_001|src_data[103]~5_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router_001|Equal3~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .lut_mask = 64'h00000000000B000B;defparam \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X19_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] &// ((!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ))) # (\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) ) #// ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & ( \u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) # ((\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout )) ) ) ) # ( \u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & !\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) ) ) ) # ( !\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout & (// !\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout & ( !\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ) ) ).dataa(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|nxt_in_ready~0_combout ),.datac(!\u0|mm_interconnect_0|cmd_mux_002|packet_in_progress~q ),.datad(gnd),.datae(!\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.dataf(!\u0|mm_interconnect_0|cmd_mux_002|last_cycle~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .lut_mask = 64'hF0F0A0A0F1F1B1B1;defparam \u0|mm_interconnect_0|cmd_mux_002|update_grant~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X19_Y35_N23dffeas \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_demux_001|src2_valid~0_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|cmd_mux_002|update_grant~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|cmd_mux_002|saved_grant[1] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( (!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2] &// !\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]) ) ) # ( !\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] ).dataa(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [2]),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARSIZE [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .lut_mask = 64'hFFFFFFFFAA00AA00;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N5dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|LessThan0~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3] &// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]// & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0] & ( (((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q// & \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg// [1])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_narrow_reg~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [1]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [3]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .lut_mask = 64'h1FFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N2dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[66] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y35_N59dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[69] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66] &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1])) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [69]),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .lut_mask = 64'h1010303010103030;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|waitrequest_reset_override~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .lut_mask = 64'h0000000000550055;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X15_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .lut_mask = 64'h00000000FF00FF00;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N32dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [0]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|wait_latency_counter [1]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .lut_mask = 64'h0000000030303030;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X15_Y35_N35dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|cp_ready~0_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .lut_mask = 64'h0F0F0F0F000F000F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ) # ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .lut_mask = 64'h0000AFFFFFFFFFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y35_N50dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y31_N39cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] &// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & (// (\u0|hps_0|fpga_interfaces|h2f_RREADY [0] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ) #// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])))) ) ).dataa(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .lut_mask = 64'h0504050455445544;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y31_N9cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .lut_mask = 64'h0505FFFF00000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y31_N11dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1]~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y31_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1] ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [1]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|read~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .lut_mask = 64'h5500FFFF00FF55FF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y31_N14dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used[0] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .lut_mask = 64'h070707070F0F0F0F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout & ( \u0|hps_0|fpga_interfaces|h2f_RREADY [0] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),.dataf(!\u0|hps_0|fpga_interfaces|h2f_RREADY [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .lut_mask = 64'h000000000000FFFF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N41dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N5dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][77]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [5]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4 .shared_arith = "off";// synopsys translate_on// Location: MLABCELL_X14_Y35_N33cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout// ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .lut_mask = 64'hFF00FF00FFF0FFF0;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N47dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~4_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N47dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]))) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2])) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg [2]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .lut_mask = 64'h1D1D1D1D00FF00FF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N23dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~7_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N17dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .lut_mask = 64'h005500550A5F0A5F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N59dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~6_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N38dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][78]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .lut_mask = 64'h000F000F303F303F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y35_N38dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~3_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78] .power_up = "low";// synopsys translate_on// Location: FF_X18_Y35_N14dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST~q ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][76]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .lut_mask = 64'h0055005522772277;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N14dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~5_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N54cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .lut_mask = 64'h0800000000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N27cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q )) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5] $ (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .lut_mask = 64'h5FA05FA0FF00FF00;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N21cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q $ (((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][77]~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .lut_mask = 64'h3CCC3CCCCCCCCCCC;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N3cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ) #// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ))) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~2_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .lut_mask = 64'h3330333003000300;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N5dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~4_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[5] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N15cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .lut_mask = 64'hA000A00000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N6cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) )// ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout// $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q )))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .lut_mask = 64'h0408070B070B0408;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N8dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~3_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[6] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N36cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6])) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]))))) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout )) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add1~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][78]~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~1_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .lut_mask = 64'h0404000015041100;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N38dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~6_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[7] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (// ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7])) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [7]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .lut_mask = 64'h00000000DFDFDFDF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N18cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_busy~q ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .lut_mask = 64'h000000000F0F0F0F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N24cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .lut_mask = 64'h00BB00BB00000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N26dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~5_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[2] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter// [3] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .lut_mask = 64'h00C300C300AA0055;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N32dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[3] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N45cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] $ (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datad(gnd),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [2]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .lut_mask = 64'h5A5A5A5AAAAAAAAA;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X13_Y35_N48cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ) ) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q $ (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ))) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][76]~q ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|Add0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][75]~q ),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][74]~q ),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .lut_mask = 64'h4411111150505050;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X13_Y35_N50dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter[4] .power_up = "low";// synopsys translate_on// Location: LABCELL_X13_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout = ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6] & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4] & (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3] &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5])) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [4]),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [3]),.datac(gnd),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [5]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|burst_uncompress_byte_counter [6]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .lut_mask = 64'h8800880000000000;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y35_N44dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] &// \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [66]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][66]~q ),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .lut_mask = 64'h0C0C3F3F0C0C3F3F;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y35_N31dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~2_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y35_N30cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ) # ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout &// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout )))) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ) # (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~0_combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~1_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|comb~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][66]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~2_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .lut_mask = 64'h00FA00FA00F800F8;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X10_Y35_N12cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & (// (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout )) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout & ((!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]))) ) ) ) #// ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout &// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0])) ) ) ) # ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout &// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]) ) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|last_packet_beat~combout ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|write~0_combout ),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.datad(gnd),.datae(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|uncompressor|always0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .lut_mask = 64'h0303CFCF01016767;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y35_N14dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1]~0_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used[1] .power_up = "low";// synopsys translate_on// Location: FF_X15_Y35_N44dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X15_Y35_N42cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout & ( (!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ) #// ((\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q )) ) ) # ( !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout & (// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ) ) ).dataa(gnd),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent|WideOr0~0_combout ),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][129]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .lut_mask = 64'h00330033F0F3F0F3;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y35_N29dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~1_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y33_N15cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout = ( \u0|mm_interconnect_0|cmd_mux_002|saved_grant [1] & ( \u0|hps_0|fpga_interfaces|h2f_ARID [11] ) ).dataa(gnd),.datab(gnd),.datac(gnd),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARID [11]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_mux_002|saved_grant [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .lut_mask = 64'h0000000000FF00FF;defparam \u0|mm_interconnect_0|cmd_mux_002|src_payload~11 .shared_arith = "off";// synopsys translate_on// Location: FF_X11_Y33_N17dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_mux_002|src_payload~11_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[116] .power_up = "low";// synopsys translate_on// Location: FF_X11_Y33_N59dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: LABCELL_X11_Y33_N57cyclonev_lcell_comb \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 (// Equation(s):// \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1] & ( \u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116] ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg [116]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[1][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [1]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .extended_lut = "off";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .lut_mask = 64'h0F0F0F0F00FF00FF;defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20 .shared_arith = "off";// synopsys translate_on// Location: FF_X14_Y35_N2dffeas \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem~20_combout ),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|always0~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116] .power_up = "low";// synopsys translate_on// Location: MLABCELL_X14_Y35_N0cyclonev_lcell_comb \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 (// Equation(s):// \u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout = ( \u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q &// (((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0])) # (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ))) ) ) # (// !\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0] & ( (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q & ((\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]) #// (\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]))) ) ).dataa(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][129]~q ),.datab(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rdata_fifo|mem_used [0]),.datac(!\u0|mm_interconnect_0|timecode_ready_rx_s1_translator|read_latency_shift_reg [0]),.datad(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem[0][116]~q ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|timecode_ready_rx_s1_agent_rsp_fifo|mem_used [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|rsp_mux_001|src_payload~56_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .extended_lut = "off";defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .lut_mask = 64'h003F003F007F007F;defparam \u0|mm_interconnect_0|rsp_mux_001|src_payload~56 .shared_arith = "off";// synopsys translate_on// Location: FF_X10_Y29_N5dffeas \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem~21_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116]~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|led_pio_test_s1_agent_rsp_fifo|mem[1][116] .power_up = "low";// synopsys translate_on// Location: FF_X21_Y31_N26dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(gnd),.asdata(\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(vcc),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X21_Y27_N51cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_mux|src_valid~0_combout = ( \u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [1] & (\u0|hps_0|fpga_interfaces|h2f_ARVALID [0] &// ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0])))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|last_channel [0]),.datab(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_rd_limiter|has_pending_responses~q ),.datad(!\u0|hps_0|fpga_interfaces|h2f_ARVALID [0]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|cmd_demux_001|src0_valid~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux|src_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .lut_mask = 64'h0000000000310031;defparam \u0|mm_interconnect_0|cmd_mux|src_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X27_Y27_N39cyclonev_lcell_comb \u0|mm_interconnect_0|router|src_data[103]~4 (// Equation(s):// \u0|mm_interconnect_0|router|src_data[103]~4_combout = ( \u0|mm_interconnect_0|router|Equal7~6_combout & ( (!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout & ((\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ) #// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout )))) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[19]~2_combout ),.datab(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[17]~1_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[18]~0_combout ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|align_address_to_size|out_data[16]~3_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|Equal7~6_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|router|src_data[103]~4_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|router|src_data[103]~4 .extended_lut = "off";defparam \u0|mm_interconnect_0|router|src_data[103]~4 .lut_mask = 64'h0000000051535153;defparam \u0|mm_interconnect_0|router|src_data[103]~4 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X28_Y27_N27cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~1 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout = ( !\u0|mm_interconnect_0|router|src_data[103]~4_combout & ( (!\u0|mm_interconnect_0|router|Equal6~0_combout & !\u0|mm_interconnect_0|router|Equal7~10_combout ) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|router|Equal6~0_combout ),.datad(!\u0|mm_interconnect_0|router|Equal7~10_combout ),.datae(gnd),.dataf(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .lut_mask = 64'hF000F00000000000;defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X28_Y27_N29dffeas \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|cmd_demux|src0_valid~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller_001|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~q ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|internal_valid~0_combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel[0] .power_up = "low";// synopsys translate_on// Location: LABCELL_X27_Y27_N42cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_demux|src0_valid~0 (// Equation(s):// \u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout = ( !\u0|mm_interconnect_0|router|Equal7~10_combout & ( !\u0|mm_interconnect_0|router|Equal6~0_combout & ( (!\u0|mm_interconnect_0|router|src_data[103]~4_combout &// (\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout & ((!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ) # (\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0])))) ) ) ).dataa(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|last_channel [0]),.datab(!\u0|mm_interconnect_0|router|src_data[103]~4_combout ),.datac(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_wr_limiter|has_pending_responses~q ),.datad(!\u0|mm_interconnect_0|hps_0_h2f_axi_master_agent|write_addr_data_both_valid~combout ),.datae(!\u0|mm_interconnect_0|router|Equal7~10_combout ),.dataf(!\u0|mm_interconnect_0|router|Equal6~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_demux|src0_valid~0_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .lut_mask = 64'h00C4000000000000;defparam \u0|mm_interconnect_0|cmd_demux|src0_valid~0 .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X11_Y27_N45cyclonev_lcell_comb \u0|mm_interconnect_0|cmd_mux|src_data[32] (// Equation(s):// \u0|mm_interconnect_0|cmd_mux|src_data [32] = ( \u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & ( (\u0|mm_interconnect_0|cmd_mux|saved_grant [0]) # (\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ) # ( !\u0|hps_0|fpga_interfaces|h2f_WSTRB [0] & (// \u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ).dataa(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),.datab(gnd),.datac(gnd),.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),.datae(gnd),.dataf(!\u0|hps_0|fpga_interfaces|h2f_WSTRB [0]),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|cmd_mux|src_data [32]),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .extended_lut = "off";defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .lut_mask = 64'h5555555555FF55FF;defparam \u0|mm_interconnect_0|cmd_mux|src_data[32] .shared_arith = "off";// synopsys translate_on// Location: LABCELL_X21_Y27_N27cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder (// Equation(s):// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout = VCC.dataa(gnd),.datab(gnd),.datac(gnd),.datad(gnd),.datae(gnd),.dataf(gnd),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .extended_lut = "off";defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .lut_mask = 64'hFFFFFFFFFFFFFFFF;defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder .shared_arith = "off";// synopsys translate_on// Location: FF_X21_Y27_N29dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~feeder_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(vcc),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y27_N21cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 (// Equation(s):// \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout = ( \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & (// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1] ) ) # ( !\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout & ( (!\u0|mm_interconnect_0|cmd_mux|saved_grant [0] &// !\u0|mm_interconnect_0|cmd_mux|saved_grant [1]) ) ).dataa(gnd),.datab(gnd),.datac(!\u0|mm_interconnect_0|cmd_mux|saved_grant [0]),.datad(!\u0|mm_interconnect_0|cmd_mux|saved_grant [1]),.datae(gnd),.dataf(!\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~0_combout ),.datag(gnd),.cin(gnd),.sharein(gnd),.combout(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),.sumout(),.cout(),.shareout());// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .extended_lut = "off";defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .lut_mask = 64'hF000F000FF00FF00;defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1 .shared_arith = "off";// synopsys translate_on// Location: FF_X18_Y27_N23dffeas \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero (.clk(\FPGA_CLK1_50~inputCLKENA0_outclk ),.d(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|WideNor0~1_combout ),.asdata(vcc),.clrn(\u0|rst_controller|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0_outclk ),.aload(gnd),.sclr(gnd),.sload(gnd),.ena(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd~combout ),.devclrn(devclrn),.devpor(devpor),.q(\u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero~q ),.prn(vcc));// synopsys translate_offdefparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .is_wysiwyg = "true";defparam \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|in_bytecount_reg_zero .power_up = "low";// synopsys translate_on// Location: LABCELL_X18_Y27_N9cyclonev_lcell_comb \u0|mm_interconnect_0|led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1.burst